Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Fuji Xerox Co., Ltd.

Satoshi Kamiya

Tatsuya Tokue

Haruya Iwata

Takayuki Mori

Sohei Kushida

Hiroshi Ichikawa

Chie Ohara

Michitomo Yamaguchi

Hiromoto Ando

Yoshimi Uezu

Daisuke Katori

Satoru Suzuki

Joi Okugi

A control device according to an embodiment includes a first region including a CPU and a sequence signal generation circuit; and a second region including an abnormality detection circuit, a sequence signal detection circuit, a first register storing multiple methods of recovery from occurrence of abnormality, and a second register for use to select one method of recovery from the multiple methods of recovery, the second region being higher in reliability than the first region. The sequence signal generation circuit converts a first signal that specifies the one method of recovery into a sequence signal containing a second signal, which is a digital signal of a predetermined pattern, and the sequence signal detection circuit changes a set value of the second register upon receiving the second signal.

Control device and method for operating control device

A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.

Control method and semiconductor integrated circuit

A semiconductor device of an embodiment includes: a power supply line and a ground line; a CMOS logic gate including a P-type MOSFET network connected to the power supply line, and an N-type MOSFET network connected to a ground line side of the P-type MOSFET network; and a P-type MOSFET and an N-type MOSFET configured to activate a parasitic capacitance of the CMOS logic gate by fixing an output signal level of the CMOS logic gate.

Semiconductor device

According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.

A semiconductor device of an embodiment includes a path monitor circuit provided in a predetermined data path in a circuit that operates with a predetermined source clock, the path monitor circuit being configured to generate an output corresponding to a degree of a timing margin, a power supply voltage control circuit configured to set a power supply voltage that is used in the circuit based on an output of the path monitor circuit, and a clock generating circuit configured to supply to the circuit a clock obtained by dividing a frequency of the source clock, based on a detection result indicating that the power supply voltage obtained based on the output of the path monitor circuit becomes lower than a predetermined threshold.

Semiconductor device and control method of semiconductor device

According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.

Clock generator and clock generation method

According to one embodiment, there is provided a semiconductor device comprising: a control circuit connected to a bus; a first circuit operating under control of the control circuit; a bus access detection circuit that detects bus access from the control circuit to the first circuit without going through the bus; a switch element connected between the first circuit and a power supply; and a second circuit connected between the first circuit and the bus, the second circuit controlling, when the bus access to the first circuit is detected by the bus access detection circuit, the switch element such that power from the power supply is supplied to the first circuit.

An image forming device that includes a communication device includes a class judging unit, a number-of-times determination unit, and a retry execution unit. The communication device transmits data to a management device through a first communication network provided by a communication carrier. The class judging unit judges a class under which a first error having occurred in data transmission falls, the class being predetermined according to a probability of a successful transmission retry. The number-of-times determination unit determines the number of times a retry is performed in response to the first error, such that the number of times the retry is performed is decreased as the probability of a successful transmission retry becomes low. The retry execution unit causes the communication device to execute the retry in response to the first error the determined number of times.

Image forming device, image forming method, and non-transitory computer readable medium

An image forming apparatus includes a selection-information acquiring unit, a type-information acquiring unit, and a selecting unit. The selection-information acquiring unit acquires selection information including information representing an additional apparatus which is selectable in accordance with a combination of one or more types of additional apparatuses connectable to the image forming apparatus. The type-information acquiring unit acquires type information representing one or more types of connecting additional apparatuses which are the additional apparatuses connected to the image forming apparatus. The selecting unit selects a connecting additional apparatus corresponding to the type information from the selection information.

Image forming apparatus, image forming system, and non-transitory computer-readable medium

Provided is an image forming device including a modifying unit that individually modifies plural items of setting information held in an own device, a specifying unit that specifies an item of the setting information which is not modified by the modifying unit, a communication unit that communicates with an external device, an acquiring unit that acquires reference setting information corresponding to each of the plural items of the setting information from the external device via the communication unit, and an updating unit that updates the item of the setting information specified by the specifying unit based on the reference setting information acquired by the acquiring unit.

Image forming device, non-transitory computer readable medium storing program, and image forming method for updating setting information

An image processing apparatus includes: an input means for inputting image data to be subjected to an image process; a storage means for storing the image data inputted from the input means; a processing means for reading out the image data stored in the storage means and subjecting the read image data to an instructed image process; an abortion means for aborting the image process of the image data performed by the processing means; a hold instructing means for giving an instruction as to whether or not the image data whose process has been aborted by the abortion means is to be continuously held in the storage means; a hold means for continuously holding the image data in the storage means based on the instruction from the hold instructing means; an execution means for reading out the image data in the storage means held by the hold means from the storage means and resuming the image process of the image data aborted by the abortion means; and a delete means for deleting the image data held in the storage means by the hold means.

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Kanagawa, Japan

Satoshi Kamiya