Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Satoshi Kaburaki

Tomoko Adachi

Tomoya Tandai

Toshihisa Nabetani

Katsuya Nonin

Masahiro Sekiya

Tetsuhiko Azuma

Kenichiro Yoshii

Kenichi Maeda

Atsushi Kunimatsu

Mitsunori Tadokoro

Nobuhiro Kondo

Ikuo Magaki

Konosuke Watanabe

Naoto Oshiyama

Katsuya Ohno

Tomonori Yokoyama

Takashi Ogasawara

Takayuki Mori

Shingo Kikukawa

Hiroshi Katougi

A memory system is connectable to the host. The memory system includes a nonvolatile first memory, a second memory in which a plurality of pieces of first information each correlating a logical address indicating a location in a logical address space of the memory system with a physical address indicating a location in the first memory are stored, a volatile third memory including a first cache and a second cache, a compressor configured to perform compression on the plurality of pieces of first information, and a memory controller. The memory controller stores the first information not compressed by the compressor in the first cache, stores the first information compressed by the compressor in the second cache, and controls a ratio between a first capacity, which is a capacity of the first cache, and a second capacity, which is a capacity of the second cache.

Memory system with first cache for storing uncompressed look-up table segments and second cache for storing compressed look-up table segments

A first memory stores a translation table indicating a first correspondence between a logical address and a physical address at first timing. A second memory stores a difference table that is configured to record, in each of entries, a correspondence between a logical address range and a physical address range, the correspondence representing a difference between the first correspondence and a second correspondence. The second correspondence is between the logical address and the physical address at second timing. In non-volatilizing data in a first logical address range to a first physical address range, in a case where the entries includes a first entry containing a correspondence between a second logical address range and a second physical address range, the controller updates the first entry. The first logical address range follows the second logical address range, and the first physical address range follows the second physical address range.

Memory system

According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory using first data. The controller is configured to write either the first data or second data into the nonvolatile memory based on a total write amount of user data into the nonvolatile memory. The second data is compressed data of the first data.

A memory system includes a memory controller and a memory that is nonvolatile. The memory controller divides first information, which correlates a logical address with a physical address of the memory, into multiple pieces of second information, attaches metadata to each of the multiple pieces of second information and stores each piece of second information with the attached metadata, into the memory, when using third information, which is one of the multiple pieces of second information, reads, as multiple pieces of fourth information, pieces of second information including the third information, from among the multiple pieces of second information stored in the memory, selects fifth information, which is different from the third information, from among the read multiple pieces of fourth information based on the metadata attached to each of the multiple pieces of fourth information, and caches the selected fifth information into another memory.

According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.

Memory system controlling a cache of a nonvolatile memory

According to one embodiment, a part of first information stored in a nonvolatile second memory is cached in a volatile third memory with a first cache line size in a case where a first memory included in a host is not used. A part of the first information is cached in the first memory with a second cache line size in a case where the first memory is used. The second cache line size is larger than the first cache line size.

Memory device and information processing device

According to one embodiment, a memory system includes a nonvolatile memory, a device controller, and a tag memory. The device controller stores a part of a logical-to-physical address translation table (L2P table) stored in the nonvolatile memory in a memory of a host as a cache. The tag memory includes a plurality of entries associated with a plurality of cache lines of the cache. Each entry includes a tag indicating which area of the L2P table is stored in a corresponding cache line, and a plurality of bitmap flags indicating whether a plurality of sub-lines included in the corresponding cache line are valid or not.

Memory system and information processing system

According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.

Memory controller, memory system and memory control method

According to one embodiment, an information processing apparatus includes a host and a memory system. The memory system includes a nonvolatile memory. The host includes a volatile memory, a first host control unit, and a second host control unit. The volatile memory includes a first area to be used by the host and a second area as a cache memory to temporarily store data of the nonvolatile memory. The first host control unit computes a first code, and stores the first data and the first code in the second area. The first code is redundant information of the first data. The second host control unit reads second data and a second code from the second area, performs error detection on the second data based on the second code, and transfers the second data. The second code is redundant information of the second data.

Information processing apparatus

According to one embodiment, a memory system includes nonvolatile memories each storing data and an address table for acquiring an address of the data, and a control unit which is configured to be capable of accessing the nonvolatile memories in parallel, and issues table read requests for reading the address tables and data read requests for reading the data to the nonvolatile memories in response to read commands from a host. When a table read request and a data read request are issued to a same nonvolatile memory, the control unit processes the data read request in priority to the table read request.

A communication method includes causing a transmitter to apply error correcting or detecting code systems to multiple frames or packets and to transmit the multiple frames or packets in succession, causing a receiver to receive the transmitted frames or packets and to decode each of the frames or packets received, and causing the receiver to send an acknowledgment signal to the transmitter on the basis of the results of decoding of the frames or packets. The transmitter applies two or more error correcting or detecting code systems to the frames or packets.

Communication method and system using two or more coding schemes

An address translation apparatus includes first to third retention units, a comparison unit, and a translation unit. The first retention unit retains a multi-bit first address. The second retention unit retains a multi-bit second address different from the first address. The third retention unit retains first information indicating which bit is a translation target in the multi bits of the first address. The comparison unit compares a multi-bit third address input from outside and the first address. The translation unit translates the bit indicated by the first information in the multi bits of the third address to obtain a fourth address such that the bit indicated by the first information coincides with the second address, when the third address coincides with the first address based on comparison result of the comparison unit.

Address translation apparatus which is capable of easily performing address translation and processor system

A wireless communication system including at least one wireless base station and two or more wireless terminals, and each of the wireless terminals can communicate with the wireless base station or directly communicate with another wireless terminal. The wireless base station observes reception frames from the wireless terminals, and transmits to one of the wireless terminals a start frame for starting direct communication of the wireless terminal concerned with another wireless terminal on the basis of the reception information of the reception frames.

Wireless base station and wireless terminal

A radio communication system in which a plurality of wireless terminals form wireless channels separately between a common base station unit and wireless terminals and communicate with the base station unit, the radio communications system comprises quality managing section manages communication quality of wireless channel for each of wireless terminals by assigning occupied band of wireless channel on basis of a predetermined parameter, channel securing section secures continuously wireless channel for at least one wireless terminal by controlling data rate of the wireless channel according to change in channel state between wireless sections, and rate change detecting section supplies trigger information to quality managing section when data rate of at least one wireless channel changes as a result of control performed by channel securing section, the quality managing section, when being given trigger, updating occupied band assigned state of the wireless channel for each of wireless terminals.

Growing community of inventors

Tokyo, Japan

Satoshi Kaburaki