Elpida Memory, Inc.

Other

Hitachi, Ltd.

Oki Electric Industry Co., Ltd.

Satoshi Itaya

Mitsuaki Katagiri

Satoshi Isa

Kayoko Shibata

Akira Ide

Shoji Azuma

Satoshi Nakamura

Takashi Suga

Dai Sasaki

Hiroki Fujisawa

Yoji Nishio

Hiroya Shimizu

Yukitoshi Hirose

Fumiyuki Osanai

Kayo Hamano

Mitsuaki Katagirl

Kei Nakakuki

Yoshiro Takahashi

A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure.

Semiconductor device and information processing system including the same

A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film.

A wiring substrate and a semiconductor chip mounted on the wiring substrate are connected together via a bonding wire. The distance from each end of the semiconductor chip to a wire bond pad provided on the wiring substrate is smaller than the height of the semiconductor chip.

Semiconductor device and method of bonding wires between semiconductor chip and wiring substrate

A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured.

A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substratesare on the upper surface of semiconductor chip. First additional wiring layer for power sourceand first additional wiring layer for groundformed on respective additional substratesform prescribed conductive areas on semiconductor chip. First power source wiringCor first ground wiringCare interconnected through additional wiring layersand. Second power source wiringCand second ground wiringC, which is extended in the same direction as with DQ system signal wiringC, forms a feedback current path. Second power source wiringCand second ground wiringCare disposed adjacent to DQ system signal wiringC.

Semiconductor device with additional power supply paths

A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

Method for designing semiconductor package, system for aiding to design semiconductor package, and computer program product therefor

A method for designing a device that comprises a first semiconductor chip, a second semiconductor chip and an adjustment target is disclosed. The first semiconductor chip comprises an input pad, a first power supply pad and a first ground pad. The second semiconductor chip comprises an output pad coupled to the input pad. The adjustment target is connected to the first and the second semiconductor chips. A main target variable is calculated from an input circuit chip model, an output circuit chip model of the second semiconductor chip in frequency domain and a target impedance model of the adjustment target in frequency domain. The input circuit chip model is created by representing the first semiconductor chip in frequency domain in consideration of a first capacitor model between the input pad and the first power supply pad, a second capacitor model between the input pad and the first ground pad, and a chip internal capacitor model between the first power supply pad and the first ground pad. The main target variable is compared with a predetermined constraint represented in frequency domain to decide design guidelines for the adjustment target.

Method for designing device, system for aiding to design device, and computer program product therefor

Disclosed is a method for manufacturing a method for manufacturing a semiconductor device which comprises a substrate, a semiconductor chip and a plurality of terminals. The method comprises preparing the substrate comprising an insulator which is formed with a plurality of signal lines, a plurality of power lines related to the plurality of signal lines and a plurality of ground lines related to the plurality of signal lines on the insulator in accordance with a predetermined layout. Each of the plurality of line groups comprises one of the power lines, one of the ground lines and one of the signal lines arranged between the one of the power lines and the one of the ground lines. Each of the plurality of line groups shares any one of the power line and the ground line with a neighboring line group of the plurality of line groups.

Method for manufacturing semiconductor device, semiconductor device and apparatus comprising same

An electronic component having a multi-layered printed circuit board made of an organic material, a plurality of electronic components mounted in a face-down position on the multi-layered printed circuit board, a metal cover for covering the plurality of electronic components remaining a space or a cavity between the top surface of the printed circuit board and the inner surface of the metal cover having a flange surrounding the outskirts of the metal cover to be adhered to the top surface of the multi-layered printed circuit board, and a heat conductive member packed between the bottom surface of the electronic components, wherein the multi-layered printed circuit board has at least one through-hole vertically penetrating the multi-layered printed circuit board at a location corresponding to the flange and is lined by a metal film, and the multi-layered printed circuit board has a heat conductive layer arranged along the rear surface of the multi-layered printed circuit board, the heat conductive layer being connected to a metal lining of the through-hole.

Growing community of inventors

Tokyo, Japan

Satoshi Itaya