Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Matsushita Electrical Industrial Co., Ltd.

Satoshi Ishikura

Yoshinobu Yamagami

Toshio Terano

Marefusa Kurumada

Toshikazu Suzuki

Hiroaki Okuyama

Hironori Akamatsu

Takayuki Yamada

Kazuo Itoh

Yukio Iijima

Hirokazu Yonezawa

Nobuaki Minakuchi

Yutaka Terada

Norihiko Sumitani

Katsuji Satomi

Atsuhiro Kajiya

Masayuki Nakamura

Takuya Umeda

A semiconductor memory includes a plurality of memory cells. The plurality of memory cells each include a latch having two inverters, where an input node and an output node of one of the inverters are respectively coupled to an output node and to an input node of the other one of the inverters, a first switch coupled in series with the latch between a first and a second power sources, and a second switch coupled in parallel with the first switch.

Semiconductor memory

A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.

Semiconductor memory device

In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.

A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.

An isolation insulating film is formed so that an active region of a first access transistor and a substrate contact region can be integrated with each other in a plan view. A dummy gate electrode is formed on the semiconductor substrate between the active region of the first access transistor and the substrate contact region. The dummy gate electrode is electrically connected to a P-type impurity region of the substrate contact region.

Semiconductor device having a SRAM with a substrate contact and method for fabricating the same

A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistorsandincluded in a latch section is different from at least one of a potential supplied to a word lineand a potential supplied to bit linesand; a latch potential control circuitfor switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pin; and a read/write control circuitfor controlling the potential supplied to the sources of the load transistorsandto be lower than at least one of the potential supplied to the word lineand the potential supplied to the bit linesand, during an arbitrary period of at least a read operation in the test mode.

A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.

Semiconductor integrated circuit

A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

Semiconductor device

A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistorsandincluded in a latch section is different from at least one of a potential supplied to a word lineand a potential supplied to bit linesanda latch potential control circuitfor switching a normal operation mode and a test mode to each other in accordance with a signal applied to a test mode setting pinand a read/write control circuitfor controlling the potential supplied to the sources of the load transistorsandto be lower than at least one of the potential supplied to the word lineand the potential supplied to the bit linesandduring an arbitrary period of at least a read operation in the test mode.

A semiconductor memory includes a plurality of memory cells, each of which includes a first inverter connected to one of high-data retaining supply lines which constitute one of high-data retaining supply line pairs corresponding to the memory cell and a second inverter connected to the other one of the high-data retaining supply lines which constitute the corresponding high-data retaining supply line pair, an input and output of the second inverter being connected to an output and input of the first inverter, respectively. A selected high-data retaining supply circuit receives a signal determined according to an input data signal and address signal without the intervention of any of the bit lines which constitute the bit line pairs to drive the connected high-data retaining supply lines such that it has a potential corresponding to the received signal.

First and second internal power source lines supply first and second voltages to an internal circuit, respectively. A first lineand a second lineare arranged parallel to the first and the second internal power source lines in a layer above the layer in which the first and the second internal power source lines are arranged. Third linesextend in a direction perpendicular to the first line in a layer above the layer in which the first and the second internal power source lines are present. Fourth linesextend in a direction perpendicular to the second line in a layer above the layer in which the first and the second internal power source lines are present. The first, and the third and the first internal power source lines are connected, and the second, and the fourth and the second internal power source lines are connected.

Repeater cells each comprising a buffer or an inverter and an n+ diffusion layer-P well type protection diode or a p+ diffusion layer-N well type antenna protection diode connected to an input pin of the buffer or the inverter for preventing antenna damage or an antenna rule error from occurring are previously registered by registration meansas the cells to be registered in a cell library. Whether or not a wiring conductor conducting to a gate electrode becomes an antenna ratio exceeding an allowed antenna ratio in the semiconductor device is determined by determination meansand if the wiring conductor exceeds the allowable antenna ratio, one or more repeater cells are inserted into any point of the wiring conductor by selection means

Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system

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Osaka, Japan

Satoshi Ishikura