Kabushiki Kaisha Toshiba

Nippon Steel Welding Products and Engineering Co., Ltd.

Inoue Denki Co., Inc.

Toshiba Microelectronics Corporation

Satoshi Inoue

Fujio Masuoka

Riichiro Shirota

Ryouhei Kirisawa

Ryozo Nakayama

Hiroshi Iwahashi

Akihiro Nitayama

Kazumasa Sunouchi

Tetsuo Endoh

Masamichi Asano

Takashi Yamada

Yasuo Itoh

Masaki Momodomi

Yuui Shimizu

Fumio Horiguchi

Hiroshi Takato

Toru Ono

Naoko Okabe

Ichiro Masuda

Yoshihisa Iwata

Kazunori Ohuchi

Shigeyoshi Watanabe

Takashi Miyamori

Masahiko Chiba

Yukio Fujiwara

A semiconductor device comprises a plurality of semiconductor chips stacked on a substrate. The semiconductor chip comprises: an internal power supply voltage generating circuit that generates an internal power supply voltage based on an external power supply; a power supply line that supplies the internal power supply voltage; an internal power supply pad connected to the power supply line; and a stabilizing capacitance connected to the power supply line. The internal power supply pad is electrically short-circuited with the internal power supply pad included in another semiconductor chip.

Semiconductor device

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell and a select gate transistor formed on a semiconductor substrate. The memory cell includes a first gate insulating film, a first charge storage layer, a first intergate insulating film, and a first control gate. The first gate insulating film, the first charge storage layer, the first intergate insulating film, and the first control gate are formed on the semiconductor substrate in order. The select gate transistor includes a second gate insulating film, a first gate electrode, a second intergate insulating film, and a second control gate. The second gate insulating film, the first gate electrode, the second intergate insulating film, and the second control gate are formed on the semiconductor substrate in order. The second intergate insulating film different first and second thicknesses.

Nonvolatile semiconductor memory device and method of manufacturing the same

A semiconductor memory device comprises a first-supplied-voltage-supplying pad, a second-supplied-voltage-supplying pad, a data input/output pad, a memory body, a buffer circuit and an impedance-controlling circuit. A first supplied voltage is supplied to the memory body. A second supplied voltage is supplied to the buffer circuit. The impedance-controlling circuit controls an impedance of the buffer circuit on a side connected to the data input/output pad. The semiconductor memory device comprises a voltage-generating circuit generating a first inner voltage. The impedance-controlling circuit comprises a first P-channel transistor. A source terminal of the first P-channel transistor is connected to the first-supplied-voltage-supplying pad, and the first inner voltage generated from the voltage-generating circuit is selectively supplied to a gate terminal of the first P-channel transistor.

Semiconductor memory device and method of testing the same

Method of production of welding wire

A multi-tier winding coil 1 of a welding wire in a hollow cylindrical configuration having a beginning wire end which is located in the innermost tier and at one of cylinder end faces, a combination of such coil with a shipment packaging box 21, and a combination of the coil 1 and a wire feed adapter 5 which is used to mount the coil on a welding machine are disclosed. The coil 1 includes bundling wires 3a-3d. The beginning wire end of the coil is bent to extend in a radial direction of the coil loop, and is then bent in a direction to extend parallel to the center axis of the coil, thus defining an L-configuration 1sr+1sa. A wire feed adapter 5 includes a barrel 5b formed with notches 5br-5br4 and 5ar-5a4 for receiving beginning ends 1s.

Bundled welding wire coil and method of bundling

The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

Non-volatile semiconductor memory and method of manufacturing the same

Method of manufacturing NAND type EEPROM

A data transfer apparatus includes a register file, a control means, and an operation defining and holding means to execute a DMA transfer of a series of data between devices at a high speed. The data, which are continuously read out from said devices, are once stored in said register file, according to the control by said control means and the information stored in said operation defining register. The data stored in said register file are then continuously transferred into the destination device. As a result, a high speed transfer of a series of data is executed between devices.

Direct memory access controller comprising a multi-word data register

An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic 'one' e.g.) in the selected cell, by applying an 'H' level voltage to the bit line, applying an 'L' level voltage to a word line connected to the selected cell, applying the 'H' level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the 'L' level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

Non-volatile semiconductor memory with NAND cell structure and switching

A light guiding plate has grooves or ridges with respective bottom or peak portions having surfaces with curvilinear sectional contours. The curvilinear portions replace angular intersections of slanted surfaces of the grooves or ridges and thereby provide uniform luminance over an entire face of the light guiding plate.

Light guiding plate

A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array. With the above construction, a short-circuiting between the embedded layers is removed and a good quality of the second inter-layer insulating film is formed.

Method of fabricating a semiconductor memory device

Semiconductor memory device and its fabricating method

In a semiconductor memory device, a storage node electrode having a cavity is provided such that the inner surface of a storage node electrode is used as a capacitor electrode. In a DRAM fabricating method, a storage node electrode having a cavity is formed by laminating a first conductor layer, an insulating film and a second conductor layer, which in turn are patterned into a desired shape, depositing a third conductor layer on the three-layer pattern, performing anisotropic etching so as to cause the third conductor layer to remain only on the side walls of the pattern to thereby form a box-shaped conductor, forming an opening in a part of the box-shaped conductor, removing the insulating film by an etching to thereby form a cavity.

MOS type dynamic random access memory

When a semiconductor device having a multi-layered contact is fabaricated, the gate electrode is covered with a thick insulator film. A polycrystalline silicon film is formed in a state in which at least the gate electrode in the contact forming area is covered with a first oxidization-proof insulator film. An inter-layer insulator film is then formed in a state in which at least part of the polycrystalline silicon film is covered with a second oxidization-proof insulator film. A first contact hole is formed using the polycrystalline silicon film as an etching stopper, and the polycrystalline silicon film is then oxidized. Furthermore, a second contact hole is formed in the inter-layer insulator film on the upper surface of the second oxidization-proof insulator film using as the etching stopper the polycrystalline silicon film underlying the second oxidization-proof insulator film. Since the polycrystalline silicon film is formed under the inter-layer insulator film in the second contact forming area so as to cover the gate electrode, it acts as a stopper when the second contact is formed to thereby prevent a short circuit with the gate electrode even if there is no distance between the gate electrode and the second contact.

Growing community of inventors

Kawasaki, Japan

Satoshi Inoue