Kabushiki Kaisha Toshiba

Sanyo Denki Co., Ltd.

Iatron Laboratories Inc.

Toshiba Memory Corporation

Mitsubishi Electric Corporation

Skhynix Inc.

Satoshi Inaba

Atsushi Yagishita

Tohru Ozaki

Akio Kaneko

Yoshiaki Matsushita

Yasushi Misawa

Yuki Onda

Yusuke Kohyama

Takashi Izumida

Nobutoshi Aoki

Yukihiro Ushiku

Makoto Fujiwara

Norihiko Tsuchiya

Kimitoshi Okano

Yasunori Okayama

Minoru Takahashi

Masanori Numano

Mitsunao Tanaka

Hiroyasu Kubota

Koji Abe

Masaharu Akimoto

Yoshiki Hayashi

Tatsuya Kishi

Takeshi Hamamoto

Ichiro Mizushima

Akira Nishiyama

Keiji Hosotani

Tatsuya Ohguro

Keisuke Nakatsuka

Atsushi Murakoshi

Hisanori Aikawa

Akira Hokazono

Masami Aoki

Kazuya Matsuzawa

Shigeru Kawanaka

Kazumasa Sunouchi

Osamu Arisumi

Masaru Toko

Kazuya Ohuchi

Yutaka Ishibashi

Naoyuki Shigyo

Makoto Yoshimi

Masakazu Goto

Tetsu Morooka

Mamoru Terauchi

Kanna Adachi

Yuki Ishimori

Yoko Suzuki

Jae Yun Yi

Hitomi Kawaguchiya

Kazuyoshi Nishidate

Kazumesa Sunouchi

Hong Ju Suh

Se Dong Kim

A linear motor includes: a mover including an output shaft portion extending in a direction of a thrust axis; a detection portion configured to be capable of detecting a position of the output shaft portion in the direction of the thrust axis; and a detected portion fixed to the mover, the mover further includes: a mounting base to which the detected portion is attached; and a metal fastening member that fastens the mounting base to an end surface, on one side in the direction of the thrust axis, of the output shaft portion, and the mounting base includes: a metal fastened portion sandwiched between the end surface, on the one side in the direction of the thrust axis, of the output shaft portion, and the fastening member; and a resin mounting portion having a mounting surface to which the detected portion is attached, the mounting surface being provided at a position off the thrust axis.

Linear motor and linear head module

A linear head module includes a plurality of linear units each having an output member, and a housing. The linear unit has a mover and a stator. The stator has an output-side bearing holder and a counter-output-side bearing holder. The housing has: a main body portion integrally including an output-side surface portion, a counter-output-side surface portion, and a coupling portion that couples the output-side surface portion and the counter-output-side surface portion; a flange facing the output-side surface portion; and a bracket facing the counter-output-side surface portion.

Linear head module

A linear head module includes: a plurality of linear motors each including a mover having an output shaft portion; a plurality of detection portions each configured to detect a position of the respective output shaft portion in a direction of a thrust axis; a single circuit board provided with the plurality of detection portions; and a detected portion provided to the respective mover, the detected portion is fixed to the mover via a mounting base, and as viewed in the direction of the thrust axis, a direction in which the mounting base extends from the output shaft portion is different from a direction in which the output shaft portion and the circuit board face each other.

A self-cooled reactor apparatus includes: a pair of frames attached to a vehicular mount, a coil disposed between the pair of frames and fixed to the frames, a cover disposed between the pair of frames, and a protective member. The coil is covered by the cover having at least a portion thereof in which through-holes are formed. The protective member, while retaining a flow passage for air from the through-holes to the coil, blocks a space between the through-hole and the coil in a penetration direction of the through-holes.

Self-cooled reactor apparatus

According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

Resistance change memory

According to one embodiment, there is provided a magnetoresistive memory device. The memory device includes active areas arranged on a semiconductor substrate, resistance change elements arrayed to matrix in an X direction and a Y direction above the substrate, and selective transistors provided to correspond to the respective resistance change elements. A plurality of gate electrodes of the selective transistors are spaced apart at regular intervals in the X direction and arranged along the Y direction. Each of the active areas is provided to cross two of the gate electrodes adjacent to each other, such as to be along the X direction at a portion crossing the gate electrodes, and formed to be inclined with respect to the X direction between the adjacent gate electrodes.

Magnetoresistive memory device and manufacturing method of the same

According to one embodiment, a semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense circuit which senses data of the memory cell based on second current that flows through the memory cell and first current, a first transistor of a first conductivity type, which is connected to the bit line and through which the second current flows, and a second transistor of the first conductivity type, through which the first current flows.

Semiconductor memory device

According to one embodiment, a semiconductor device includes a semiconductor substrate having a trench and including an active area including a channel area formed along an inner surface of the trench and source/drain areas formed at both ends of the channel area and sandwiching the trench, a gate insulating film formed on the inner surface of the trench, and a gate electrode formed in the trench in which the gate insulating film is provided. A main surface of the semiconductor substrate has {100} plane orientation, a portion of the channel area parallel to a side surface of the trench has {110} channel plane orientation and has &#x3c;100&#x3e; channel orientation in a channel length direction, and tensile stress in the channel length direction and compressive stress in a channel width direction are applied to the portion of the channel area parallel to the side surface of the trench.

Semiconductor device including buried-gate MOS transistor with appropriate stress applied thereto

According to one embodiment, a semiconductor device includes a semiconductor substrate with a groove for forming an embedded gate therein, and a gate electrode embedded via a gate insulator film in the groove. A portion of the semiconductor substrate near the gate electrode is doped with a chemical element which is inactive in the semiconductor substrate.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device that has a rectification element includes a semiconductor substrate, a first well region of a first conductivity type formed on the semiconductor substrate, a second well region of a second conductivity type formed on the semiconductor substrate, and a plurality of fins arranged over the first well region and the second well region at a first pitch in the same direction. In the semiconductor device, the rectification element includes a cathode region, an anode region, a well contact region, and a trigger region that are configured using fins. These regions are connected to each wiring portion to form a PNP-type bipolar transistor and an NPN-type bipolar transistor.

Semiconductor device

According to one embodiments, a transparent reference electrode is provided to be sandwiched between a red-detecting photoelectric conversion film and a green-detecting photoelectric conversion film, a first transparent driving electrode is provided to face the transparent reference electrode with the green-detecting photoelectric conversion film therebetween, a second transparent driving electrode is provided to face the transparent reference electrode with the red-detecting photoelectric conversion film therebetween, and a blue-detecting photoelectric conversion film is provided below the red-detecting photoelectric conversion film and performs blue detection.

Solid-state imaging device

In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.

A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.

The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Semiconductor device and method of manufacturing semiconductor device

A method of fabricating a semiconductor device according to one embodiment includes: forming a mask material on a semiconductor substrate comprising first and second regions; forming a pattern of a core on the mask material in the first region; forming a sidewall spacer mask on a side surfaces of the core pattern and subsequently removing the core pattern; transferring a pattern of the sidewall spacer mask to the mask material in the first region after removing the core; and thereafter, carrying out trimming of the pattern of the sidewall spacer mask which is transferred to the mask material in the first region, and formation of a predetermined pattern on the mask material in the second region, simultaneously.

Method of fabricating semiconductor device, and photomask

Growing community of inventors

Yokohama, Japan

Satoshi Inaba