Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Corporation

Satoshi Iida

Masaaki Shinohara

Masahiro Moniwa

Fumihiko Nitta

Yoshihiro Kusumi

Masamichi Matsuoka

Takahiro Mori

Nobuo Fujiwara

Tetsuhiro Fukao

Makoto Koshimizu

Shigenori Sakamori

Shigeo Tokumitsu

Junjiro Sakai

Kazunori Yoshikawa

Shinya Kato

Yoshinori Fujii

Yoshiki Maruyama

Takahiro Yokoi

Hiroshi Miyatake

Hiroki Aoki

Yuki Murayama

Yuki Miyazaki

Akihiro Hanawa

Tomo Inoguchi

Toshihide Sugihara

Yuji Mizuno

There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.

Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Method of manufacturing semiconductor integrated circuit device

Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film.

Described is a semiconductor device having a buried multilayer wiring structure, in which there is ensured good conductivity among a plurality of wiring layers. A lower wiring pattern is formed from conductive material, and an upper wiring pattern is formed from conductive material. Insulating layers are provided between the lower wiring pattern and the upper wiring pattern. A connection section is formed so as to penetrate through the insulating layers to thereby establish continuity between the lower and upper wiring patterns, as well as to have a greater cross-sectional area at the end facing the upper wiring pattern and a smaller cross-sectional area at the end facing the lower wiring pattern.

Semiconductor device, and manufacturing method therefor

Provided are a method for manufacturing contact structure to prevent, in the wire of a borderless structure, erosion in the contact area between the wire and a conductor. An interlayer insulating film (300) having a wire burying hole is formed and a conductor (400) is buried in the hole. Then, a wire layer (500) covering the hole is formed on the interlayer insulating film (300). The wire layer (500) is made so as to have a borderless structure by using a resist (540) as a mask. A barrier metal layer (510) suppresses erosion in the contact area between the conductor (400) and the wire layer (500).

Method for manufacturing contact structure

An interconnection layer 3 in a floating state and an interlayer insulating film 6 are formed on a semiconductor substrate. A connection hole 4 penetrating the interlayer insulating film and the interconnection layer is formed by dry etching with fluorocarbon. Filled in the connection hole is a conductive member 5 which is electrically connected to the interconnection layer. Accordingly, an improved method for manufacturing a semiconductor device offering a reduced contact resistance even for an extremely small contact hole is obtained.

Method of manufacturing semiconductor device

Growing community of inventors

Tokyo, Japan

Satoshi Iida