Sharp Kabushiki Kaisha Corporation

Satoshi Hikida

Takuya Otabe

Hisashi Yonemoto

Norihiro Tokuyama

Kazuhiko Yoshino

Shuhji Enomoto

Yuji Fukui

In the method of manufacturing a semiconductor apparatus of the present invention, after forming trench isolation regions, andon a surface of a semiconductor substrateso as to isolate element regions on which the semiconductor elements are to be formed, a silicon nitride film (antioxidant film)is formed so as to cover the trench isolation regions and to stick out from the trench isolation regions with partially overlapping element regions adjacent to the trench isolation regions, and a thermal oxide filmthat is thicker than a thermal oxide film required in a semiconductor element of a predetermined size among a plurality of semiconductor elements, is formed on the element region using the antioxidant film as a mask.

Method of manufacturing a semiconductor apparatus and electronic equipment

The present invention provides a high breakdown voltage transistor that eases an electric field concentration caused between a gate and a drain. The present invention provides a semiconductor device comprising: a first gate electrode formed above a semiconductor substrate through a gate insulating film; a second gate electrode that is formed above the semiconductor substrate through the gate insulating film, and that is arranged at the side of the first gate electrode through an insulating spacer; a source region and a drain region formed on the semiconductor substrate so as to sandwich the first and second gate electrodes; and an electric-field concentration easing region that is formed to sandwich some region of the semiconductor substrate below the first gate electrode, and that is formed to be overlapped with the second gate electrode and the source and drain regions.

Semiconductor device, and its manufacturing method

A semiconductor device having an MOSFET serving as an element to be protected, and an electrostatic protection MOSFET element mounted on the same substrate is produced with the small number of steps while implementing a high protection ability. Low concentration regions and gate electrodes are formed and then an insulation film is formed on a whole surface. Then, etching is performed using a resist pattern as a mask to leave the insulation film in a region from a part of the gate electrode to a part of the low concentration region in each of regions Aand A, and on a side wall of the gate electrode in a region A. Then, a high concentration ion implantation is performed using the gate electrodes and the insulation films as masks, and then a silicide layer is formed.

Semiconductor device and method for manufacturing the same

A high breakdown voltage MOS transistor capable of reducing a leakage current while reducing an element size as compared with conventional ones is realized. On a P type well, with a channel area ch in between, an N type first impurity diffusion area including a drain area and drain side drift area, and an N type second impurity diffusion area including a source area and a source side drift area are formed. Moreover, a gate electrode is formed, via a gate oxide film, above a part of the first impurity diffusion area, above the channel area and above a part of the second impurity diffusion area. The gate electrode is doped with an N type, and an impurity concentration of portions located above the first and the second impurity diffusion areas is lower than an impurity concentration of a portion located above the channel area.

Semiconductor device having gate electrode with lower impurity concentration at edge portions than above channel and method of manufacturing the same

The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.

Semiconductor device comprising high-withstand voltage MOSFET and its manufacturing method

In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an active region demarcated by the element isolating region; a gate electrode formed on the semiconductor substrate in the active region by having a gate insulating film in between; a channel region arranged in the semiconductor substrate under the gate electrode; a source region and a drain region positioned on the both sides of the gate electrode; and a drift region positioned between one of or both of the source region and the drain region and the channel region. One of or both of the source region and the drain region are at least partially positioned on the element isolating region, and are connected with the channel region through the drift region.

Small size transistor semiconductor device capable of withstanding high voltage

A semiconductor device comprises a first conductive film formed downward, perpendicular to a substrate, penetrating through a first insulating film, a second conductive film formed downward along an outer wall of a second insulating film, a third insulating film formed from the bottom of the second conductive film to the top of the substrate in an area sandwiched between the first and second insulating films, contacting with at least the bottom of the second conductive film and an outer wall on a side which does not contact with the second insulating film, and a first impurity diffusion area of a first conductivity type, a second impurity diffusion area of a second conductivity type, a third impurity diffusion area of the first conductivity type and a fourth impurity diffusion area of the first conductivity type in a high concentration layered within the area sandwiched between the first and third insulating films.

Vertical MOS transistor device with asymmetrical source and drain and its manufacturing method

A method of producing a semiconductor device having a LDD structure using a semiconductor substrate laminated with an insulating film, a polysilicon layer, and a first conductive layer where the first conductive layer is formed of a high melting point metal and the first conductive layer and polysilicon layer are removed in the region other than a gate pattern formation region but without exposing the insulating layer. After implanting the semiconductor substrate with a first impurity, the residual polysilicon layer in the region other than the gate pattern formation region along with a polysilicon layer sidewall in the gate pattern formation region are converted into a silicon oxide layer by subjecting to oxidation treatment, and the semiconductor substrate is laminated with a second conductive layer. Subsequently, the second conductive layer is removed by anisotropic etching so as to remain only on the sidewall of the gate pattern formation region, and the semiconductor substrate is then implanted with a second impurity to form source and drain regions.

Manufacturing method of semiconductor device

A silicon oxide film is formed at a surface of a silicon substrate of a first conductive type, and then patterned to have an opening. PSG is deposited on the silicon substrate having the insulating film thereon, and then etched to leave the PSG only on a side wall of the opening. An impurity is implanted to the silicon substrate through the opening, and then thermal treatment is effected.

Method for producing the bipolar transistor

A method for manufacturing a semiconductor device including forming an epitaxial layer on a second conductive silicon substrate selectively provided with a first conductive impurity diffusion layer and diffusing a second impurity through surface of the epitaxial layer to form islands of the epitaxial layer, the above epitaxial layer having a higher specific resistance than that of the silicon substrate.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device wherein in the case where a Bi transistor and a CMOS transistor are to be formed on a first conductive semiconductor substrate, a gate oxide film on an active base in a Bi transistor formation region is partially removed by a predetermined pattern so as to form the opening of the gate oxide film, a polysilicon layer having second conductive impurities doped at a high density is patterned over the edge of the opening, and the emitter region of the Bi transistor is formed from the portion in which the active base comes into contact with the first conductive semiconductor substrate, i.e., from the gate edge and the edge of the opening of the gate oxide film to the portion in which the gate oxide film comes into contact with a gate, prior to the steps of determining a transistor formation region by an isolation oxide film, thermally oxidizing the whole surface of the semiconductor substrate including the isolation oxide film, injecting first conductive impurities as the active base in the Bi transistor formation region and forming the polysilicon layer having the second conductive impurities doped at the high density at the gate of the CMOS transistor.

Growing community of inventors

Osaka, Japan

Satoshi Hikida