Fujitsu Corporation

Satoshi Furuta

Shigenori Yanagi

Toru Fujiwara

Masakazu Taguchi

Kenichi Hamada

Masaharu Moritsugu

Tadashi Sagawa

Akihiro Itakura

Akira Minami

Shigeyoshi Tanaka

Akira Nanba

Shuko Saito

Katsuhiko Fukuda

An information recording and reproduction apparatus has a turbo decoder that decodes turbo encoded data. The turbo decoder has a number of likelihood ratio calculation units, forward direction path probability calculation units the number of which is less than the number of the likelihood ratio calculation units, and backward direction path probability calculation units the number of which is less than the number of the likelihood ratio calculation units. The likelihood ratio calculation units calculate in parallel the likelihood ratio for each of a plurality of data blocks. The forward direction path probability calculation units time-divisionally calculate probabilities of the forward direction paths for the data blocks. The backward direction path probability calculation units time-divisionally calculate probabilities of the backward direction paths for the data blocks.

Information recording and reproduction apparatus, optical disk apparatus and data reproduction method

A power supply control device is provided with a first power supply input terminal to which a power supply is provided and a second power supply input terminal to which a power supply is provided. A power supply input detection unit detects an instance when the input of the second power supply input terminal is above a predetermined value and then a switch unit cuts off power supplied from the first power supply input terminal and activates power supply from the second power supply input terminal when the input from the second power supply input terminal is above a predetermined value according to the power supply input detection unit. A power supply processor processes a power supply supplied by way of the first or second power supply input terminal.

Method for providing priority to an ac adaptor if the input to the ac adaptor is above a predetermined value even if the power supply via an interface is present

A clock adjustment apparatus for adjusting a phase of a clock signal based on a phase error thereof is provided in a data reproduction system which samples a readout signal from a recording medium in synchronism with the clock signal, and reproduces data in accordance with a Viterbi algorithm by using sampled values of the readout signal. The recording medium is recorded with the data modulated in accordance with a recording rule of a predetermined partial response characteristic. The clock adjustment apparatus includes a phase error calculation circuit which calculates the phase error of the clock signal based on the sampled values of the readout signal.

Apparatus for adjusting phase of clock signal based on phase error calculated from sampled values of readout signal

A data reproduction apparatus includes first and second sampling parts which sample a reproduced signal from a recording medium in synchronism with first and second clock signals synchronizing respectively with leading and trailing edges of the reproduced signal and output leading and trailing sampled values, respectively, and a combination part which generates combined sampled values based on the leading and trailing sampled values. Recorded data is reproduced based on transition states of the combined sampled values output from the combination part in accordance with a maximum likelihood decoding technique corresponding to a predetermined partial response waveform.

Data reproduction apparatus, data recording and reproduction apparatus, and method for reproducing recorded data

A data recording method for calculating a digital sum value (DSV) corresponding to a proportion of positive data and negative data included in predetermined data ranges, selecting a resync pattern to be inserted between the data ranges according to the DSV, and inserting the selected resync pattern between the data ranges, has a step of selecting a resync pattern that minimizes differences in DSV between the data ranges.

Data recording method and apparatus for reducing fluctuation in DC component

In a data reproducing apparatus, a monitor edge sample value is generated based on a second sample value at a trailing edge of the reproduction signal and a change amount of the monitor edge sample value is generated as an offset amount in a first processing part. Then, the offset amount is supplied to a second processing part where the second sample value is obtained by sampling the reproduction signal at the trailing edge. Then, the second processing part restores data based on the reproduction signal and the offset amount.

Clock adjusting device for use with data reproducing apparatus, offset detecting device, and data reproducing apparatus

A data reproduction system, which determines reproduced data based on comparison results of path metrics calculated in accordance with a Viterbi algorithm based on branch metrics calculated from expected values and a sampled value of a readout signal, includes an expected value setting unit for variably setting the expected values used for a calculation of the branch metrics in order to perform a Viterbi detection process without being easily affected by the transient response, offset variation, phase error and nonlinear torsion component of the readout signal. The readout signal is obtained from a recording medium on which data is recorded in accordance with a recording signal of a partial response waveform, the expected values are determined by the partial response waveform, and the sampled value is obtained by sampling the readout signal at a predetermined frequency.

System for reproducing data with increased accuracy by reducing difference between sampled and expected values

A clock matching apparatus for a data reproduction system includes a phase error detection unit which detects a phase error of a clock signal based on samples of a readout signal output by a sampler of the data reconstruction system. A phase-locked loop supplies a phase-matched clock signal to the sampler by compensating for the phase error detected by the phase error detection unit. The phase error detection unit includes an edge detection unit which detects a sampling instant for an edge sample among the samples of the readout signal. A difference unit generates a difference in timing phase between the edge sample and a sync level, the sync level being a reference signal level corresponding to a level of the readout signal at the sampling instants thereof and defined based on a partial-response waveform, the difference in the timing phase being output to the phase-locked loop as the detected phase error.

Clock matching apparatus for a data reproduction system

An optical disk apparatus adapted to a mark edge recording method having a structure such that a data pattern experimentally recorded on an optical disk with one write power is reproduced plural times while changing reproducing conditions (for example, a slice level for binary-coding a reproduced analog signal) and the number of errors is calculated whenever the reproducing process is performed. The thus-structured process is repeated for using a plurality of write powers. An appropriate write power for the optical disk is determined in accordance with the obtained results of the calculations of the number of errors. In a case of a read-only optical disk, a data pattern experimentally and previously recorded on the optical disk is reproduced plural times by changing the reproducing conditions (for example, a slice level for binary-coding a reproduced analog signal), and the number of errors is calculated whenever the reproducing process is performed. In accordance with the obtained results of the calculations of the number of errors, an appropriate reproducing condition for the optical disk is determined.

Optical disk having write power adjustment portion

Optical disk apparatus

An encoding unit encodes data to be recorded on a recording medium. The encoding unit includes a first part for inserting resynchronizing bytes between two data blocks within a data field when converting data coded by a predetermined modulation code which generates patterns having D.C. components into pulse width modulation data, where the resynchronizing bytes have resynchronizing patterns and achieve synchronization when a clock slip occurs within the data field, a second part for calculating a digital sum value for a predetermined data block, where the digital sum value indicates a difference between a sum total of logic values '1' and a sum total of logic values '0' in the pulse width modulation data, and a third part for controlling the first part so that the resynchronizing bytes having resynchronizing patterns that minimize the digital sum value is inserted in a present data block.

Encoding unit and storage unit using the same

An optical disk apparatus which is servo-controlled to trace a track according to a servo signal wherein the track is optically and selectively writable, readable and erasable according, respectively, to write, read and erase pulses of light emitted into the track. The optical disk apparatus includes a pulse edge detection mechanism which outputs an edge detection signal upon detecting an edge of a writing pulse or an edge of an erasing pulse, a masking pulse forming mechanism which generates, in response to the edge detection signal, a masking pulse used for disabling the servo signal during the masking pulse so as to prevent an erroneous servo signal caused from a switching transient of the writing pulse or the erasing pulse, and a pulse duration setting mechanism, receiving clock pulses as an input, for setting a pulse duration of the masking pulse by counting the clock pulses. The pulse duration setting mechanism includes a counter to count the clock pulses wherein a count number of the counter is presettable.

Growing community of inventors

Kato, Japan

Satoshi Furuta