Fujitsu Corporation

Buffalo Inc.

Fujitsu Vlsi Limited

Satoru Yamaguchi

Hitoshi Takahashi

Yoshihiro Morita

Hideo Nunokawa

Yutaka Ito

Masato Kato

Kunihiko Wada

Noriaki Sato

Daisuke Yamada

Hiroshi Katano

Mamoru Yokoyama

Hiroyuki Izui

Seishiro Hamanaka

Nagahiro Matsuura

Michihiko Koseki

Katsumi Yagita

Naoya Matsumoto

Hitoshi Takahaski

Sadayoshi Taniwaki

Masashi Sumi

A transmitting apparatus for transmitting user data, includes: an establishing section that establishes three or more transmission paths for a receiving apparatus; a first generation section that generates a user data unit which includes user data to be transmitted to the receiving apparatus; and a second generation section that generates an error correction data unit which includes error correction data to be used for error correction of the user data to be transmitted to the receiving apparatus. At least one of the three or more transmission paths transmits the error correction data unit, and at least two of the three or more transmission paths transmits the user data unit.

Transmitting apparatus and transmission method

A relay device first uses latest authentication data to determine whether request-authentication data transmitted from a wireless communications device is valid. If the latest authentication data is used to determine that the request-authentication data is valid, the relay device carries out relayed communications with the wireless communications device. If the latest authentication data is used to determine that the request-authentication data is invalid, the relay device next uses a former authentication data to determine whether the request-authentication data is valid. If the former authentication data is used to determine that the request-authentication data is valid, the relay device provides the wireless communications device with the latest authentication data to update authentication data in the wireless communications device.

Relay device, wireless communications device, network system, program storage medium, and method

A data processing system having an efficient logging mechanism which stores log records for repairing a file system when its consistency is lost. When there is a transaction attempting to update metadata stored in metadata volumes, a metadata loading unit reads the requested metadata objects out of the volumes and loads them to a metadata cache. At that time, a metadata manager updates its internal database to record from which metadata volume each metadata object has been fetched. Each time the transaction updates a metadata object in the cache, a log collection unit collects a copy of the updated metadata object, together with a volume ID which indicates its home metadata volume. The collected data is temporarily stored in a log buffer, and finally saved into a log volume by a log writing unit.

Data processing system with mechanism for restoring file systems based on transaction logs

The present invention writes intrinsic information such as the current time, etc. to both a memory and a storage medium when an exchangeable storage medium inserted in a drive device is mounted to a system. If the storage medium is removed from the drive device when the storage medium is being I/O accessed, then the execution of the present and the succeeding I/O requests is suspended. Then, if a storage medium is inserted in the drive device, then it is checked whether or not the intrinsic information stored in the memory has been written to the storage medium. Only when the information has been written to the storage medium, the suspended request for the storage medium is resumed. Accordingly, even if a storage medium has been erroneously removed from the drive device, all I/O requests are surely executed without being lost if the erroneously removed medium is inserted again. Furthermore, the data in a replacing storage medium won't be erroneously lost, either. The stop of power supply for a drive device is permitted only when a storage medium is not mounted to a system. Therefore, all I/O requests for the storage medium have been executed, and the data in another storage medium are not lost when power supply is resumed with another storage medium inserted during the suspension of the electric power supply.

Data protecting system for an echangeable storage medium comprising

A storage section stores therein one or more files each composed of a plurality of data blocks each having a constant length. A plurality of buffers are provided corresponding to the plurality of blocks. A batch block demand section generates a batch block input demand for batch inputting the plurality of blocks of the storage section. A batch transfer processing section performs an input process of the plurality of blocks between the batch block demand section and the plurality of blocks, and at the same time performs the input process of the plurality of blocks between the plurality of buffer and the storage section.

System for batch transfer file management using a list to organize a

A microprocessor has a memory part including a memory for storing programs, a central processing unit for carrying out an operation on a data stored in the memory part depending on the programs stored in the memory, a holding part for entering an address region information with a predetermined timing and for holding the address region information, which indicates an allocation of a predetermined address region for the memory, an address generating part for generating an address of a command which is to be executed next, and an access enable part for enabling access to the memory when the address generated by the address generating part is included in the predetermined address region.

Single-chip microprocessor having variable memory address mapping

A programmable semiconductor read only memory device which includes a memory cell array formed by a plurality of memory cells arranged in a matrix arrangement. Each memory cell in the memory cell array includes a transistor having a gate thereof coupled to a word line, and a capacitor having an insulator layer, having a first terminal coupled to a bit line and having a second terminal coupled to the transistor so that the capacitor is grounded via the transistor. The insulator layer of the capacitor of a selected memory cell breaks down when a specific word line and a specific bit line coupled to the selected memory cell are driven, thereby making the capacitor conductive.

Programmable semiconductor read only memory device

A write circuit for an EPROM device of a microcomputer comprises a first circuit responsive to an external clock signal WCLK and machine clock signals for supplying a clock signal CLK to a program counter of the microcomputer so as to successively increment an address produced in the program counter, where the external clock signal WCLK has a frequency lower than those of the machine clock signals and the clock signal CLK has different frequencies during normal and write-in operation modes so that the address produced in the program counter is successively incremented in synchronism with the machine clock signals during the normal operation mode and is successively incremented in synchronism with the external clock signal WCLK during the write operation mode, and a second circuit responsive to the machine clock signals and a bit data of a LSB of the address from the program counter for generating a bit line clock signal BCLK for inhibiting a write-in data from being written into the EPROM device during a time period in which the address changes.

Write circuit for an erasable programmable read only memory device of a

An input circuit having a plurality of channels, each channel includes a conductor line, first and second transistors inserted in series into the conductor line and a third transistor. When a channel is not selected, the first and second transistors are turned off and the third transistor is turned on to clamp the conductor line at a predetermined constant voltage. When a channel is selected, the third transistor is turned off and first and second transistors are turned on to transfer the corresponding information input therethrough.

Multiplexing input circuit

A boosting circuit includes a plurality of variable capacitors with controllable capacitance values in accordance with the voltage level at first and second terminals of each of the variable capicitors A plurality of first buffer circuits is located at the first terminal side, each acting to increase the voltage level at the corresponding first terminal to a first level. A single second buffer circuit located at the second terminal side cooperating commonly with the variable capacitors, to increase the voltage level at each second terminal. The first level is thus boosted to a second level which results in an output of the circuit concerned. Each variable capacitor is fabricated by a MOS transistor capacitor.

Growing community of inventors

Nagoya, Japan

Satoru Yamaguchi