Seiko Epson Corporation

Satoru Uematsu

Kunio Tabata

Noritaka Ide

Dai Nozawa

Rika Tanimoto

A drive circuit includes a modulation circuit that modulates a base drive signal that is a base of a drive signal for driving a drive section, and outputs a modulation signal, an amplification circuit that outputs a first amplified modulation signal obtained by amplifying the modulation signal, a level switching signal generation circuit that generates a level switching signal as a digital signal including a first potential and a second potential, a level shift circuit that outputs the first amplified modulation signal as a second amplified modulation signal, and outputs, as the second amplified modulation signal, a signal obtained by shifting a potential of the first amplified modulation signal, and a demodulation circuit that demodulates the second amplified modulation signal, and outputs the drive signal. The level switching signal generation circuit switches a potential of the level switching signal in response to the base drive signal and the modulation signal.

Drive circuit and liquid ejecting apparatus

A drive circuit includes a modulation circuit that modulates a base drive signal, and outputs a modulation signal, an amplification circuit that outputs a first amplified modulation signal obtained by amplifying the modulation signal, a level switching signal generation circuit that generates a level switching signal, a level shift circuit that outputs the first amplified modulation signal as a second amplified modulation signal when the level switching signal has the first potential, and outputs, as the second amplified modulation signal, a signal obtained by shifting a potential of the first amplified modulation signal when the level switching signal has the second potential, and a demodulation circuit that demodulates the second amplified modulation signal. A threshold when the level switching signal generation circuit switches from the first potential to the second potential is different from a threshold when switching from the second potential to the first potential.

A drive circuit includes a modulation circuit that outputs a modulation signal, an amplification circuit that outputs a first amplified modulation signal obtained by amplifying the modulation signal, a level switching signal generation circuit that generates a level switching signal, a level shift circuit that outputs the first amplified modulation signal, or outputs a signal obtained by shifting a potential of the first amplified modulation signal, and a demodulation circuit that demodulates a second amplified modulation signal output by the level shift circuit, and outputs the drive signal, a feedback circuit that outputs a feedback signal to the modulation circuit, and a stop time duration measurement circuit that outputs a stop time duration measurement signal in response to the modulation signal. The level switching signal generation circuit switches a potential of the level switching signal in response to the base drive signal and the stop time duration measurement signal.

A liquid ejecting apparatus includes an ejecting unit that ejects liquid when a drive signal is supplied to the ejecting unit, a drive signal output unit that outputs the drive signal, a cooling unit that cools the drive signal output unit, and a power supply unit that supplies power to the cooling unit. The liquid ejecting apparatus has a first mode in which the drive signal output unit outputs a first drive signal of a first frequency, and a second mode in which the drive signal output unit outputs a second drive signal of a second frequency lower than the first frequency. An amount of power supplied by the power supply unit to the cooling unit in the first mode is larger than an amount of power supplied by the power supply unit to the cooling unit in the second mode.

Liquid ejecting apparatus

There is provided a liquid discharge apparatus including: a discharge section; a first wiring for transmitting a setting information signal group that has a first setting information signal and a second setting information signal and a discharge control signal group; and a second wiring for transmitting a driving signal, in which the apparatus is configured to be operated in a first print mode in which printing is performed with a first gradation number according to the setting information signal group, and in a second print mode in which printing is performed with a second gradation number smaller than the first gradation number, and in the second print mode, the droplets are discharged from the discharge section according to the first setting information signal and the second setting information signal in which bit data of the first setting information signal is inverted.

Liquid discharge apparatus

There is provided a liquid discharge apparatus including: a first shift register; a plurality of discharge sections configured to discharge droplets based on head control data; and a first wiring for transmitting the head control data to the first shift register, in which the apparatus is configured to be operated in a first print mode in which printing is performed with a first gradation number, and in a second print mode in which printing is performed with a second gradation number smaller than the first gradation number, based on the head control data, in the first print mode, a data size of the head control data is a sum of a first data size, a second data size, and a third data size, and in the second print mode, a data size of the head control data is a sum of the first data size and the second data size.

A semiconductor integrated circuit having an internal SRAM that includes a plurality of arrayed memory cells, including a first bit line and a second bit line that are connected to first ports and a third bit line and a fourth bit line that are connected to second ports of the memory cells, a first and second transistor respectively compose first ports of adjacent first and second memory cells and having shared impurity diffusion region connected to the first bit line via a first interconnection, a third transistor composing a second port of the first memory cell and having an impurity diffusion region connected to the third bit line via a second interconnection a fourth and fifth transistor respectively composing the first ports of the first and second memory ceils and having a shared impurity diffusion region connected to the second bit line via a third interconnection.

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Minehara Shiojiri, Japan

Satoru Uematsu