Renesas Electronics Corporation

Fujitsu General Limited

Satoru Tokuda

Atsushi Sakai

Katsumi Eikyu

Hiroshi Yanagigawa

Satoshi Uchiya

Hiroyoshi Kudou

Akihiro Shimomura

Tomofumi Kawai

Syun Iwano

Ryuuji Umemoto

Yuta Nabuchi

A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.

Semiconductor device and method of manufacturing the same

A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

Semiconductor device

A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; a first wiring and a second wiring disposed on the first surface; a first conductive film electrically connected to the first wiring; and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The drift region is disposed so as to surround the body region in a plan view. The first wiring has a first portion disposed so as to extend across a boundary between the drift region and the body region in a plan view, and electrically connected to the drift region. The second wiring is electrically connected to the source region. The first conductive film is insulated from and faces the second wiring.

Air-blowing from a second air outlet is effectively used. An air conditioner includes a main body unit and an auxiliary housing. The main body unit forms a first air outlet which blows out a cool or warm airflow. The auxiliary housing is attached to at least one side of the first air outlet to be freely movable, and forms a second air outlet which blows out taken-in indoor air. A control circuit blows out the indoor air from the second air outlet at a wind speed which is higher than the wind speed of cool air or warm air that is blown out of the first air outlet.

Air conditioner and control circuit

The present invention provides a semiconductor device that can reduce effects of noise without complicating processes or increasing chip area. The semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a drain region, a drift region, a base region, a source region, a gate electrode, an interlayer insulating film, a conductive layer electrically coupled to the drain region, a wiring line, and a contact plug electrically coupled to the source region and the wiring line. The interlayer insulating film has an intermediate interlayer insulating film. The intermediate interlayer insulating film is arranged between the conductive layer and the contact plug. The intermediate interlayer insulating film is a thermal oxide film of a material that forms the conductive layer.

A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is &#x2267;90% and &#x2266;110% of the depth of the first concave portion. The thickness of LIL2 is &#x2267;95% and &#x2266;105% of the thickness of LIL1. The UIF is thicker than the GIF.

Growing community of inventors

Hitachinaka, Japan

Satoru Tokuda