Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Satoru Tanigawa

Atsuhisa Kageyama

Hisao Kunitani

Ryuichi Shibutani

Hiroshi Sonobe

Takashi Koizumi

Nobuko Fujita

A contour correcting device which includes a plurality of delay elements which delay an input video signal, a pixel-selection-control-signal generation circuit, a pixel selection circuit which selects outputs of the plurality of delay elements in response to outputs of the pixel-selection-control-signal generation circuit, a high-pass filter operation circuit and an adder circuit which adds an operation result of the high-pass filter operation circuit to the input video signal. When the pixel selection circuit extracts a contour component in a boundary portion between a horizontal video effective period and a period other than the horizontal video effective period of the input video signal, the pixel selection circuit replaces pixel data in the period other than the horizontal video effective period among pixel data input to the high-pass filter operation circuit, with pixel data at an edge-point of the horizontal video effective period.

Contour correcting device, contour correcting method and video display device

The motion detection device includes an oblique correlation detection section, a motion detection section and a motion determination section. The oblique correlation detection section detects a correlation in an oblique direction (oblique correlation) of a composite video signal. The motion detection section detects a motion amount based on an inter-frame difference of the composite video signal. The motion determination section determines the presence/absence of a motion in the composite video signal based on the motion amount detected by the motion detection section. The motion determination section determines the presence/absence of the motion considering the detection results of the oblique correlation by the oblique correlation detection section.

Motion detection device and method, luminance/chrominance signal separation device and method, noise reduction device and method, and video display device and method

To improve accuracy of determining the average brightness level and maximum and minimum levels of the brightness signals for the entire screen. There are included a differential operation circuit that detects and differentiates rise or breaking edges in horizontal and vertical synchronous signals of an input image signal, thereby outputting horizontal and vertical differential signals synchronized with the horizontal and vertical synchronous signals, respectively; a sample window circuit that detects the beginning and ending positions of horizontal and vertical intervals to produce sample window signals established in any desired vertical and horizontal positions on the screen in accordance with the horizontal and vertical differential signals; and a brightness signal output circuit that outputs sampled brightness signals when the sample window circuit is operative.

Brightness signal processing apparatus

A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set value for every reference clock, extracting data according to the cumulative value, converting the data into an analog signal, reducing quantization noise, and multiplying the analog signal, thereby to obtain a second clock; and a clock switch circuit for generating a sync signal that is switched to the second clock, by using a sync signal generated with the first clock; and video signal processing is carried out using the second clock that is generated according to the resolution of a pixel display.

Video signal processing apparatus which generates plural clocks and performing video signal processing using the plural clocks

A format conversion apparatus for subjecting data having a predetermined resolution to conversion of the resolution according to a resolution of a display screen, comprises: a timing generation unit for generating a timing for thinning out inputted signal data, using a resolution conversion coefficient that is calculated on the basis of a conversion ratio of the resolution; and a selection unit for selecting, from two pieces of input signal data existing before and after the timing generated by the timing generation unit, the signal data that is timewise closer to the timing; wherein resolution conversions in the horizontal direction and the vertical direction are carried out while maintaining the combination of the inputted signals.

Format conversion apparatus, format conversion method, and image display apparatus and image display method using the format conversion apparatus

In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

Semiconductor device

A video signal processor and a video signal processing method which can prevent the length of one period of a clock from being shortened and can output a video signal that is in phase with a reference signal. When a video data signal that has been processed using a first clock signal is processed using a second clock signal, this video signal processor does not utilize as the second clock signal, a clock signal that is in phase with a reference signal but a clock signal that is employed in a later stage signal processor, and interpolates the video data signal by an interpolation circuit so as to make the signal in phase with the reference signal.

Video signal processor and video signal processing method which interpolate a video signal using an interpolation factor based on phase information of a selected clock

An oblique correlation detection section detects correlation in an oblique direction (oblique correlation) of a composite video signal. A line correlation chrominance separation section extracts a first chrominance signal from the composite video signal based on vertical correlation of the composite video signal. A first chrominance signal acquisition section acquires a second chrominance signal based on horizontal self-correlation of the first chrominance signal. The first chrominance signal acquisition section detects the self-correlation within a range corresponding to the degree of the oblique correlation detected by the oblique detection section.

Video signal processing device and method

A luminance signal/chrominance signal separation apparatus is provided with a detector for detecting diagonal components of a luminance signal from a composite video signal, wide-band pass filters, and narrow-band pass filters, wherein band pass filters to be connected to a three-line chrominance separation circuit are selected according to the amount of diagonal components of the luminance signal, thereby reducing cross color and improving resolution.

Luminance signal/chrominance signal separation device, and luminance signal/chrominance signal separation method

A video signal processing apparatus comprises a sub-screen processing integrated circuit for subjecting a sub-screen video signal to scale-down processing to reduce its display region and output the sub-screen video signal, and a main-screen processing integrated circuit comprising: a switching circuit for receiving a main-screen video signal and the scaled-down sub-screen video signal which is outputted from the sub-screen processing integrated circuit, and selecting the main-screen video signal for a main-screen display region while selecting the sub-screen video signal for a sub-screen display region; an A/D conversion circuit for converting the video signal outputted from the switching circuit into a digital video signal; a digital signal processing circuit for digitally processing the digital video signal outputted from the A/D conversion circuit; and a D/A conversion circuit for converting the digitally-processed video signal into an analog video signal. Therefore, the main-screen video signal and the sub-screen video signal can be combined so that these signals are displayed on a single screen, and the circuit scale of the video signal processing apparatus can be minimized.

Video signal processing apparatus

A video signal processing apparatus A comprises: an adder for generating a second address value S which has a predetermined phase difference from a first address value S outputted by an address value output means and outputting the same; a selector for selecting either a first address value S or a second address value S to output as an output signal S ; a vertical synchronizing signal output means for outputting the vertical synchronizing signal S to the selector ; a ROM for outputting first data corresponding to the first address value S or second data corresponding to the second address value S as a signal S ; a loading hold mode flip-flop for preserving the first data; a loading hold mode flip-flop for preserving the second data; and a hue adjustment means B which adjusts the hue of the video signal by using the output signal S of the loading hold mode flip-flop and the output signal S of the loading hold mode flip-flop . Therefore, a video signal processing apparatus which can reduce a circuit size with maintaining performance can be provided.

Growing community of inventors

Kawanishi, Japan

Satoru Tanigawa