Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Satoru Tamada

Tatsuya Saeki

Yuichi Kunori

Hidenori Mitani

Fumihiko Nitta

Yasuhiro Kouro

Kei Maejima

Satoshi Tatsukawa

A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.

Nonvolatile semiconductor memory device having reduced dependency of a source resistance on a position in an array

The number of times of rewriting of memory cells is stored by number of rewrite (EW) times storage section. In data rewriting to memory cells, number of rewriting times data of a selected memory cell is transferred to and latched in a number of EW times sense latch section and transferred to a number of EW times counter. Controlling processor (CPU) sets a condition on a write pulse on the basis of a value obtained by updating a count value of the number of EW times counter and controls the operation of rewriting. In data rewriting, a count value after update of the number of EW times counter is transferred to the number of EW times sense latch section. The updated number of rewritings is transferred to a corresponding number of EW times storage section, in parallel to data rewriting to a memory cell.

Non-volatile semiconductor memory device

A non-volatile semiconductor memory device includes, a plurality of word lines, a plurality of bit lines, a plurality of memory circuits, and a reading circuit. A plurality of bits are memorized at each memory cell. The plurality of bit lines lie at right angle to the word lines. The reading circuit is configured to read certain data from every (n&minus;1)th (n is an integer that is greater than two) memory cell of a memory cell array that is connecting to at least a word line. The memory cell exists on the point of intersection with the word line and the bit line. Then data reading and data writing are made by applying the voltage on the word line and the bit line. The non-volatile semiconductor memory device is electrically rewritable.

Non-volatile semiconductor memory device configured to read data at a high speed

There is provided a non-volatile semiconductor device having a memory cell in which a threshold value voltage changes in accordance with the application of the writing pulse having a predetermined width and voltage with respect to word lines and bit lines and data depending upon the threshold value voltage is written, wherein writing failure is generated in the first time data writing operation, and a writing condition is set for suppressing the writing condition is set which is capable of suppressing the writing failure rate than the case of the first time writing operation when the writing operation is re-executed.

Non-volatile semiconductor memory device capable of suppressing writing and erasure failure rate

To provide a semiconductor memory capable of executing a read test at a high speed based on a comparatively complicated test pattern without increasing a circuit area. Every fifth node N of a latch L of a sense latch group is connected to a gate of an NMOS transistor QLi (i&equals;0 to 3) at 4 intervals and every fifth node N is connected to a gate of an NMOS transistor QRi at 4 intervals. The NMOS transistor QLi has a drain connected to a decision result line CHKiL and a source grounded. The NMOS transistor QRi has a drain connected to a decision result line CHKiR and a source grounded. An ALL deciding circuit A outputs, as a decision result ALL , decision result signals ALL L to ALL L obtained from decision result lines CHK L to CHK L and decision result signals ALL R to ALL R obtained from decision result lines CHK R to CHK R.

Semiconductor memory

In a memory cell array having sub-bit lines and sub-source lines formed of a diffusion layer, a main bit line is arranged commonly to the sub-bit lines arranged in multiple columns. A memory cell area can be reduced without restrictions by pitch conditions of the main bit lines.

Nonvolatile semiconductor memory device having an array structure suitable to high-density integrationization

The inventive flash memory comprises a memory cell array including nonvolatile memory cells and a control CPU controlling data writing, reading and erasing in the memory cell array and a multivalued flag part. The multivalued flag part stores a value indicating whether data written in any memory cell is binary data or multivalued data. The data can be read in a binary read sequence for the binary data or a multivalued read sequence for the multivalued data due to the value of the multivalued flag part.

Nonvolatile semiconductor memory device having structure storing multivalued data and data storage system comprising the nonvolatile semiconductor memory device

Growing community of inventors

Tokyo, Japan

Satoru Tamada