Tdk Corporation

Headway Technologies, Incorporated

Sae Magnetics (h.k.) Limited

Satoru Sueki

Yoshitaka Sasaki

Hiroyuki Ito

Tatsuya Harada

Nobuyuki Okuzawa

Hiroshi Ikejima

Ryuji Hashimoto

A method of manufacturing a layered chip package that includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of layer portions. The method includes fabricating a plurality of substructures, and completing the layered chip package by fabricating the main body using the plurality of substructures and by forming the wiring on the main body. Each substructure is fabricated through the steps of: fabricating a pre-substructure wafer including a plurality of pre-semiconductor-chip portions aligned; distinguishing between a normally functioning pre-semiconductor-chip portion and a malfunctioning pre-semiconductor-chip portion among the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer; and forming electrodes connected to the normally functioning pre-semiconductor-chip portion and having respective end faces located in the side surface of the main body on which the wiring is disposed, without forming any electrode connected to the malfunctioning pre-semiconductor-chip portion.

Method of manufacturing layered chip package

A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include specific pairs of layer portions. Each of the specific pairs of layer portions includes a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. The specific pairs of layer portions are provided in an even number.

Layered chip package with wiring on the side surfaces

A layered chip package includes: a plurality of layer portions stacked, each of the layer portions including a semiconductor chip; and a heat sink. Each of the plurality of layer portions has a top surface, a bottom surface, and four side surfaces. The heat sink has at least one first portion, and a second portion coupled to the at least one first portion. The at least one first portion is adjacent to the top surface or the bottom surface of at least one of the layer portions. The second portion is adjacent to one of the side surfaces of each of at least two of the plurality of layer portions.

Layered chip package with heat sink

A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed.

Layered chip package

A layered chip package has a main body including pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The pairs of layer portions include at least one specific pair of layer portions including a first-type layer portion and a second-type layer portion. The first-type layer portion includes electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. A layered substructure formed of a stack of two substructures, each of which includes aligned preliminary layer portions, is used to fabricate a stack of a predetermined two or greater number of pairs of layer portions, and the main body is fabricated by stacking an additional first-type layer portion together with the stack, the number of the additional first-type layer portion being equal to the number of the specific pair(s) of layer portions included in the stack.

A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.

Layered chip package and method of manufacturing same

A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces.

A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. To manufacture the layered chip package, a layered chip package substructure is fabricated by: processing a semiconductor wafer to form a plurality of pre-semiconductor-chip portions aligned; forming at least one groove extending to be adjacent to at least one of the pre-semiconductor-chip portions; forming an insulating layer to fill the groove; and forming the electrodes.

A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure; bonding the first pre-polishing substructure to a jig such that a first surface of the first pre-polishing substructure faces the jig; forming a first substructure by polishing a second surface of the first pre-polishing substructure; bonding the second pre-polishing substructure to the first substructure such that a first surface of the second pre-polishing substructure faces the polished surface of the first substructure; and forming a second substructure by polishing a second surface of the second pre-polishing substructure.

A layered chip package includes: a main body including a plurality of layer portions; wiring disposed on a side surface of the main body; a plurality of first terminals disposed on a top surface of the main body; and a plurality of second terminals disposed on a bottom surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions, and to the plurality of first and second terminals.

A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes a plurality of first-type layer portions each including a first-type semiconductor chip; and a second-type layer portion including a second-type semiconductor chip. The first-type semiconductor chip includes a plurality of memory cells. The second-type semiconductor chip includes a control circuit that controls writing and reading on and from the memory cells included in the plurality of first-type layer portions. Each layer portion includes an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. Each of the electrodes has an end face that is located at the side surface of the main body and connected to the wiring.

Growing community of inventors

Tokyo, Japan

Satoru Sueki