Nec Corporation

Satoru Sonobe

Hideo Abe

In the test, the semiconductor memory device capable of error correction is tested to judge whether or not errors which exceed the correction ability of the error correction occur in the memory section of the device. As a result of the test, the semiconductor memory device in question is judged normal when errors occurring therein do not exceed the correction ability. The device subjected to the test is determined not to have any serious problem, even if it includes any errors, since such errors are always corrected by error correction of the device. Thus, according to this invention, the yield of the semiconductor memory device drastically can increase.

Testing method of semiconductor memory device and semiconductor memory device applicable to the method

To increase access speed, a single-chip computer system having a direct memory access (DMA) mode, includes a central processing unit (CPU) for executing instructions, a first bus connected to the CPU, a memory array connected to the first bus, for storing data, a buffer connected to the first bus, a second bus connected to the buffer, and a communication circuit, connected to the second bus, for receiving and outputting data. The buffer connects the first bus to the second bus when the DMA mode is executed, and disconnects the first bus from the second bus when the DMA mode is not executed.

Direct memory access (DMA) via separate bus utilizing a buffer for

A data processor has a memory 100 for storing instructions being connected to a microcomputer 10 having a function of fetching an instruction from an external memory 100 via an external bus 95, a plurality of peripheral input/output circuits 40 via 49 incorporated in the microcomputer 10, and each of the peripheral input/output circuits 40 via 49 being interconnected by an incorporated peripheral bus 90, a bus controller 30 in the microcomputer 10 having both a bus state counter 31 for the external bus and a bus state counter 32 for the incorporated peripheral bus and independently controlling an external bus cycle using the external bus 95 and an incorporated peripheral bus cycle using the incorporated peripheral bus 90.

Data processor having bus controller for controlling a plurality of

A data processing system includes a microprocessor and a memory coupled to each other, and has a burst access function in which, when an active burst request signal is supplied to the memory, only a first address is outputted to the memory, so that a plurality of items of data are accessed sequentially from the first address. A memory region of the memory is divided into a plurality of memory blocks, and the microcomputer includes a register for storing burst access/single access information for each of the memory blocks, and a decoder receiving an address to be outputted to the memory for knowing to which memory block a memory region to be accessed belongs. When the memory region to be accessed is a memory block for the burst access, a burst request signal is activated.

Data processing system having microprocessor-based burst mode control

A semiconductor memory circuit includes a plurality of memory cells arranged in an array form, a plurality of data lines for reading and writing data, a plurality of address lines each for transferring an address signal that specifies a corresponding specific memory cell, a control unit for controlling reading and writing of the data, a plurality of data input and data output terminals for inputting and outputting the data, a write enable signal input terminal to which a write enable signal for permitting writing of the data is applied, and at least one control signal input terminal to which either a cell clear signal for clearing the data stored or a cell initialization signal for performing the initialization of the data is applied. Data reading, data writing and data clearing or data initializing are performed through the plurality of data lines and the plurality of address lines. The hardware area to be occupied is reduced due to a reduction in the number of the cell transistors and also by a reduction in the number of signal lines.

Semiconductor memory circuit having bit clear and/or register initialize

This variable clock dividing circuit is provided with a plurality of dividers coupled in succession. A first of the dividers divides the basic clock by a predetermined dividing ratio and provides an output clock signal to the next divider in succession, while the last divider receives an output clock signal from the next to last divider. The dividing circuit selectively outputs one of the output block signals from the dividers using a switching circuit. A phase synchronization circuit synchronizes the phase of the clock input to the plurality of dividers based on the basic clock. The phase synchronization circuit further comprises a buffer to delay the basic clock before inputting it to the first divider, and a plurality of AND gates. Each of the AND gates corresponds corresponds to the second to last dividers and receives the basic clock and the outputs from all the preceding dividers.

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Tokyo, Japan

Satoru Sonobe