Canon Kabushiki Kaisha

Satoru Shingai

Takeru Ohya

Kenichi Nishimura

Yukio Araoka

Toshiki Tsuboi

Shoji Takada

Yuta Okabe

A first imaging device and a second imaging device are configured to directly receive a signal from a trigger generation circuit. A processing device processes first image data captured by the first imaging device in response to a first trigger signal, and second image data captured by the second imaging device in response to a second trigger signal. The first trigger signal and the second trigger signal are signals generated to start capturing images at the same time point. The processing device performs recognition processing of a target included in the first image data and the second image data.

Imaging system

A system includes one or more edge devices an integrated management apparatus configured to manage the one or more edge devices. The edge devices include a photodetector. The integrated management apparatus manages a first trained model and a first condition in association with each other. The first condition sets a condition for a photodetector used in generating the first trained model. The integrated management apparatus is configured to deliver the first trained model and the first condition to the edge devices.

System and edge device

A first lateral surface, a second lateral surface, an upper surface, and a bottom surface of a housing of an imaging device is formed of metal and at least two surfaces among the first lateral surface, the second lateral surface, the upper surface, and the bottom surface include a groove region formed of a plurality of grooves.

Imaging device and imaging system

A solid-state image sensor comprising a pixel array having a plurality of pixels, and a plurality of signal processing circuits each of which amplifies a signal of the pixel array, wherein each of the plurality of signal processing circuits comprises an operation amplifier having an input terminal and an output terminal, an input capacitance arranged between the input terminal and the column signal line, and a feedback circuit which connects the input terminal with the output terminal, wherein the feedback circuit is configured to form a feedback path in which a first and a second capacitance elements are arranged in series in a path connecting the input terminal to the output terminal, and a third capacitance element is arranged between a reference potential and a path connecting the first capacitance element to the second capacitance element.

Growing community of inventors

Machida, Japan

Satoru Shingai