Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Satoru Saitoh

Shinichi Yamada

Hiroyuki Honma

Hideki Kano

Tomoyoshi Fujimori

Taiji Ema

Satoshi Eto

Masahito Tomizawa

Kazuto Nishimura

Masato Takita

Masahiro Suzuki

Takuya Ohara

Takashi Honda

Masahiro Shioda

Osamu Takeuchi

Masatomo Hasegawa

Shigeki Aisawa

Yoshitaka Taki

Masashige Kawarai

Koji Hachiya

Yoshiyuki Karakawa

Junichi Kawaguchi

Takuma Shoji

Yuji Kuroki

Masaki Bansho

Koichi Masuda

Tamon Shinmoto

There is provided an optical transmission device including a light source configured to generate light used for coherent detection processing of reception light; a monitor configured to monitor a frequency offset between the reception light having a plurality of protection wavelengths and the light generated by the light source, based on a signal obtained by the coherent detection processing of the reception light having the plurality of protection wavelengths available for a work wavelength by the light generated by the light source; and a controller configured to select a protection wavelength to be switched to the work wavelength among the plurality of protection wavelengths, based on the frequency offset monitored by the monitor.

Optical transmission device and protection wavelength selection method

A transmission apparatus includes: a frame transmitter configured to receive an asynchronous first frame transmitted via a first transmission network and arrange the received first frame to a second frame to transmit the arranged second frame to a second transmission network; a congestion detector configured to detect congestion that has occurred in an asynchronous transmission apparatus that receives the first frame via the first transmission network; and a band controller configured to control a transmission band of a path so as to reduce the transmission band of a path on the second transmission network corresponding to a path on which the congestion has occurred.

Transmission apparatus and method for controlling transmission band

In an apparatus for accommodating and multiplexing asynchronous client signals in which an idle signal is defined, the transmission side transmits client signals after synchronizing the client signals by inserting or removing, with reference to a specific client signal, an idle signal to/from the same type of another client signal, and in the receiving side, a PLL part is shared by recovering a clock from a client signal and distributing the clock for another client signal.

Client signal accommodating multiplexing apparatus and method

In a destuff circuit, after invalid data included in each data signal assigned to a plurality of lanes in a stuff shifter is collected to one side within the same column, then in a data rotator the number of stuffs of the respective data signals of each column is detected, and the data of the respective columns are operated to rotate in one direction, according to the detection results. Then, effective data included in the data signal of each lane that has been rotated is stored in FIFO, to thereby output signals for which ineffective data has been removed and only effective data has been extracted. As a result, it becomes possible to perform destuffing processing for parallel data signals with simple logical circuits at high speed.

Destuff circuit and transmission device

A redundancy control method is disclosed that controls a first redundancy function that switches between a working line and a protection line in response to a detection of a line error and a second redundancy function that performs a path switching in response to a detection of a path error in a ring network operating at a path rate lower than a line rate thereof. The method comprises a step of masking the path error detection within a period from a time of the detection of the line error to an expected time of the detection of the path error.

Method for controlling redundancy and transmission device using the same

In a path status monitoring method and device which can enhance or reduce a band more rapidly, for example, SONET frames FR serially connected over 32 frames to which frame Nos. FN ('0'-'31')) are assigned are cyclically generated respectively for paths P-Pin a cycle T(=64 ms). After output timing delays T-Tof the frames FR are shifted by an optimal delay interval D (=21 ms) between the paths P-Pbased on the number of the paths &#x201c;3&#x201d;, the output timing delays Tand Tare restored by preliminarily obtained transmission delays for the paths Pand Pto the path P. When the frames FR are transmitted through each of the paths P-P, statuses (path statuses MST) where a reception fault has occurred in each of the paths P-Pare collected to be stored in the frame whose frame No. FN=&#x201c;0&#x201d;.

Path status monitoring method and device

The present invention discloses a method for controlling a physical bandwidth of a ring-based network by employing a ring application of a data link layer that operates in a physical layer. The method includes the steps of a) requesting each of a plurality of node apparatuses included in the ring-based network to confirm whether the bandwidth can be changed, b) instructing each node of the apparatuses to prepare for the bandwidth change upon receiving a confirmation that the bandwidth can be changed, c) reporting that the preparation for the bandwidth change is completed, and d) changing the bandwidth by using a bandwidth changing function of the ring application upon receiving the report of the completion of the preparation for the bandwidth change.

Bandwidth controlling method and node apparatus for a ring-based network

A signal distribution method and a signal distribution apparatus are disclosed, wherein transport packets of a television signal containing multiplexed channels are provided in a transmission format of a digital broadcasting standard, and such transport packets are transmitted and distributed over a synchronous network. Transmission rate (data speed) of the transport packets of a given customer in the synchronous network is selectable based on the number of multiplexed channels for the customer.

Signal distribution method and a signal distribution apparatus

When an externally received data frame is transmitted at a station of a ring-shaped packet communication network, a congestion point in the communication network is defined as a boundary point, a frame addressed to a station located before the boundary point is transmitted at a first transfer rate, and a frame addressed to a station located after the boundary point is transmitted at a second transfer rate lower than the first transfer rate.

Node device configuring ring network and data frame control method

A write-bank selecting unit selects different memory banks in response to N+1 consecutive write requests, respectively. In each memory cycle, a data writing unit inputs N or less write commands to a data access unit. On the other hand, a primary read-bank selecting unit selects readable memory banks in each memory cycle. A secondary read-bank selecting unit selects memory banks corresponding to read requests for which data blocks could not be read out in the preceding memory cycle. A data reading unit generates read commands for those read banks and inputs the generated read commands to a data access unit. With this configuration, a packet buffer capable of satisfying both of short processing cycles and high memory use efficiency can be provided by using memory devices at a relatively low price.

Packet buffer

A delay circuit and a plurality of accepting circuits are comprised. The input signal supplied from exterior is delayed for a predetermined length of time by the delay circuit, and then it is distributed and output to the plurality of the receiver circuits. The delay time of the delay circuit is adjusted to optimize an accepting timing to an input signal by a clock signal in each of the accepting circuit. The each accepting circuit reliably accepts the delayed input signal respectively in synchronization with a clock signal. Therefore, it is unnecessary to respectively provide a delay circuit in the plurality of the accepting circuits. As a result, the plurality of accepting circuits can reliably accept input signals without enlarging a circuit scale. A plurality of delay circuits, a plurality of accepting circuits, and an operating circuit are comprised. The delay circuit receives a plurality of input signals, and outputs each of the delayed input signals respectively to the plurality of accepting circuits. The accepting circuit accepts the delayed input signals in synchronization with a clock signal. More than one of the delayed input signals are supplied to the operating circuit to perform a logic operation. The delay time of the each delay circuit, for example, is in accordance with the supplying timing to the input signal supplied to the operating circuit. As a result, the operating circuit performs the logic operation with a sufficient timing margin.

Semiconductor integrated circuit including command decoder for receiving control signals

A semiconductor integrated circuit device has a data holding section for storing information, a counter for counting the number of externally applied pulses, and a comparison/verification section. The comparison/verification section compares an output of the counter with an output of the data holding section, and verifies whether the outputs match or not. This configuration serves to reduce the number of wiring lines formed from pads to a comparison/verification circuit (a signature circuit), and thereby achieves a reduction in layout area and facilitates efficient layout work.

Semiconductor integrated circuit device capable of reading out chip-specific information during testing and evaluation

A DRAM semiconductor device is provided which includes a semiconductor substrate, a field insulating film formed on the semiconductor substrate, a plurality of active regions in the semiconductor substrate, each surrounded by the field insulating film, a gate electrode traversing each of the plurality of active regions, a pair of source/drain regions formed in each of the plurality of active regions on both sides of the gate electrode, a plurality of bit lines extending along one direction, each connected to one of the pair of source/drain regions, a plurality of word lines extending along a direction perpendicular to the bit lines, each of the plurality of word lines being connected to the gate electrode, and a plurality of capacitor elements extending over said gate electrode each connected to the other of the pair of source/drain regions, wherein each of the plurality of active regions includes an oblique area formed obliquely relative to the bit and word lines and a parallel area formed in parallel to the bit line and having a width greater than the width of the oblique area, and each of the word lines has a bent portion intersecting substantially at a right angle with the oblique area of each of the active regions.

DRAM semiconductor device including oblique area in active regions and its manufacture

Connections of global data buses GDB,and GDB,to local data buses LDB,to LDB,in a bank,are reverse to those in a bank,. That is, the global data bus GDB,is connected to every other local data bus LDB,, LDB,and LDB,including both sides in the bank,, and to every other local data buses LDB,and LDB,excluding both sides in the bank,, while the global data bus GDB,is connected to every other local data buses LDB,and LDB,excluding both sides in the bank,, and to every other local data bus LDB,, LDB,and LDB,including both sides. Further, bit line patterns obliquely traversing sense amplifier rows are reverse to each other with respect to the banks,and

Semiconductor memory device having multi-bank and global data bus

A semiconductor memory device, in which the output is restored to high impedance state and capable of operating always normally even when a prohibited command is input thereto, is disclosed. The device has a common terminal for data input and output, and data are output in synchronism with a clock. The device further comprises an output clock generating circuit for generating a clock in accordance with the output period of the output data, and an output circuit for producing the output data in accordance with the clock. The output clock generating circuit is turned off after generating an additional two cycles of the clock following the end of the production of the output data.

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Kawasaki, Japan

Satoru Saitoh