Semiconductor Energy Laboratory Co., Ltd.

Satoru Ohshita

Kazuki Tsuda

Yoshiyuki Kurokawa

Hiromichi Godo

Hidefumi Rikimaru

Kouhei Toyotaka

Hitoshi Kunitake

Daisuke Kubota

Tatsuya Onuki

Satoru Okamoto

A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.

Memory device and method for manufacturing the same

A semiconductor device having a novel structure is provided. The semiconductor device includes memory layers and a driver circuit layer. The memory layers are stacked over the driver circuit layer and each include a memory cell array including a plurality of memory cells. Writing or reading of data to or from one of the memory cells is controlled with a write word line, a read word line, a write bit line, and a read bit line. The driver circuit layer includes a driver circuit portion configured to drive the write word line, the read word line, the write bit line, and the read bit line; and an arithmetic circuit portion. The driver circuit portion includes a plurality of driver circuits configured to control data writing or reading on the memory cell array basis. The arithmetic circuit portion is a circuit configured to perform arithmetic processing using the data retained in the memory cell array provided in each of the memory layers and read through the driver circuit portion.

Semiconductor device

To provide a novel electronic device. The electronic device includes a housing and a display device. The display device includes a first layer, a second layer, and a third layer. The first layer, the second layer, and the third layer are provided in different layers. The first layer includes a driver circuit and an arithmetic circuit. The second layer includes pixel circuits and a cell array. The third layer includes light-receiving devices and light-emitting devices. The pixel circuits each have a function of controlling light emission of the light-emitting device. The driver circuit has a function of controlling the pixel circuits. The arithmetic circuit has a function of performing arithmetic processing on the basis of first data corresponding to currents output from the light-receiving devices and second data corresponding to a potential held in the cell array.

Electronic device

A high-resolution display apparatus having a function of sensing light is provided. The display apparatus includes a display portion in which a first arrangement pattern and a second arrangement pattern are repeatedly arranged in this order in a first direction. In the first arrangement pattern, a first subpixel, a second subpixel, and a third subpixel are repeatedly arranged in this order in a second direction. In the second arrangement pattern, a fourth subpixel and a fifth subpixel are repeatedly arranged in this order in the second direction. The first to fourth subpixels each include a light-emitting device. The fifth subpixel includes a light-receiving device.

Display apparatus including light-emitting device and light-receiving device

A semiconductor device with low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first gate and a first back gate, and the second transistor includes a second gate and a second back gate. A gate insulating layer for the first back gate has ferroelectricity. The first transistor has a function of, when being in an off state, retaining a first potential corresponding to first data. The second transistor has a function of making an output current flow between a source and a drain of the second transistor.

Semiconductor device and electronic device

A novel semiconductor device is provided. A structure body extending in a first direction, a first conductor extending in a second direction, and a second conductor extending in the second direction are provided. In a first intersection portion where the structure body and the first conductor intersect with each other, a first insulator, a first semiconductor, a second insulator, a second semiconductor, a third insulator, a fourth insulator, and a fifth insulator are provided concentrically around a third conductor. In a second intersection portion where the structure body and the second conductor intersect with each other, the first insulator, the first semiconductor, the second insulator, a fourth conductor, the second semiconductor, and the third insulator are provided concentrically around the third conductor.

An electronic device having an eye tracking function is provided. The electronic device includes a display device and an optical system. The display device includes a first light-emitting element, a second light-emitting element, a sensor portion, and a driver circuit portion. The sensor portion includes a light-receiving element. The first light-emitting element has a function of emitting infrared light or visible light. The second light-emitting element has a function of emitting light of a color different from that of light emitted from the first light-emitting element. When the first light-emitting element emits infrared light, the light-receiving element has a function of detecting the infrared light that is emitted from the first light-emitting element and reflected by an eyeball of a user. When the first light-emitting element emits visible light, the light-receiving element has a function of detecting the visible light that is emitted from the first light-emitting element and reflected by the eyeball of the user. The first light-emitting element and the second light-emitting element are placed in one layer. The layer where the first light-emitting element and the second light-emitting element are positioned overlaps with the sensor portion.

A memory device with a small number of wirings using a NAND flash memory having a three-dimensional structure with a large number of stacked memory cell layers is provided. A decoder is formed using an OS transistor. An OS transistor can be formed by a method such as a thin film method, whereby the decoder can be provided to be stacked above the NAND flash memory having a three-dimensional structure. This can reduce the number of wirings provided substantially perpendicular to the memory cell layers.

Memory device and electronic device

A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory cells each provided with a writing transistor, a reading transistor, and a capacitor. An oxide semiconductor is used in a semiconductor layer of the writing transistor. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, information stored in the memory cell is read out.

Memory device

A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.

Growing community of inventors

Atsugi, Japan

Satoru Ohshita