Hitachi, Ltd.

Other

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Usli Systems Co., Ltd.

Satoru Nakanishi

Kazumasa Yanagisawa

Toshio Sasaki

Takao Watanabe

Takashi Miyamoto

Hitoshi Tanaka

Kazushige Ayukawa

Yuji Tanaka

Jun Sato

Mariko Ohtsuka

Yoshihiko Yasu

Takao Okubo

Masamichi Kishi

Shigeru Kadowaki

Shigeru Suzuki

Hironori Iwasaki

Manabu Inoue

Yasuro Kubota

A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.

Semiconductor device

A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing &plus;1 or &minus;1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

Semiconductor integrated circuit device

A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

A non-volatile memory, such as a flash memory card, using a rewritable non-volatile memory is provided with an improved write-protect arrangement. The non-volatile memory includes a collectively electrically erasable and writable memory (e.g., a flash memory), a reset IC for generating a power-on reset signal upon turn-on of the power supply, and a card controller for performing control between each flash memory device and a memory card interface. The flash memory is set with a write protect save register written with an address of an area desired to be subjected to write protect, the write protect save register belonging to an attribute area, and a protect range is set from the system. Since the address to be write-protected is itself written in the non-volatile flash memory, the address will continue to be stored, even if the power is turned off. A method for software write protection control is also provided.

Non-volatile memory, memory card and information processing apparatus

Growing community of inventors

Fuchu, Japan

Satoru Nakanishi