Nippon Precision Circuits Inc.

Other

Satoru Miyabe

Kazuhisa Oyama

Kunihiko Tsukagoshi

Yasuhiro Sugimoto

Minoru Takeda

Akira Toyama

The first amplifier circuit D is formed by connecting drains of a pair of N-channel MOS transistors forming the first current mirror circuit CM respectively to the drains of P-channel MOS transistors and as a differential input portion, and the second amplifier circuit D is formed by connecting drains of a pair of P-channel MOS transistors forming the second current mirror circuit CM respectively to the drains of N-channel MOS transistors and as a differential amplifier circuit. The first and second differential amplifier circuits D and D can amplify the first and second signals having cycles corresponding with each other with their duty ratios kept unchanged regardless of their operating point potentials. Further, the two outputs are combined into one output to suppress variation of the operating point potential of the output attributable to process-related factors, fluctuation of the power supply potential due to the oscillating operation and the like.

Differential amplifier circuit

To restrain cycle-to-cycle jitter in a clock generator subjected to EMI a 2 order PLL having a loop filter including a first capacitor and a first resistor, is provided where a reduction in a comparison frequency is avoided by using a clock modulating circuit. The clock modulation circuit is controlled by an intermediary signal provided by dividing an oscillation signal of a voltage controlled oscillator. The output of the clock modulation circuit is used to recurrently control a divider for dividing the output of the voltage controlled oscillator. Generation of high frequency noise is minimized by using a 1 order &Dgr;&Sgr; modulator( ) in the clock modulation circuit. The system behaves like a 3 order PLL due to the presence of a second capacitor having a capacitance value of about {fraction (1/10)} or more than that of the first capacitor. The second capacitor is placed in parallel with the loop filter to restrain the cycle-to-cycle jitter by effectively removing the high frequency noise.

Spread spectrum type clock generating circuit

To provide a cascode amplifying circuit having large amplifying gain without narrowing an output operational range or deteriorating response performance of the circuit even with a constitution by a small number of elements is achieved by applying negative feedback from the source to the gate of an MOS transistor M provided with an output terminal at the drain via the source and the drain of an MOS transistor M of N-channel type, the source and the drain of an MOS transistor M of P-channel type and a current mirror constituted by MOS transistors M and M of N-channel type. By this constitution, operation of the MOS transistor M is not effected with influence of lowering of voltage of the source of the MOS transistor M a wide output operational range is provided and mirror effect with respect to gate/drain capacitance of the MOS transistor is restrained to thereby restrain a reduction in response speed.

Cascode amplifying circuit and folded cascode amplifying circuit

In a sample-and-hold circuit using a completely differential type operational amplifier circuit, to promote operational stability, to restrain a variation in a balance point of a middle value of differential output signals and to promote stability and accuracy of an A/D converter are achieved by a constitution as bellow. There is provided a common phase feedback circuit common phase feedback hold capacitors CF and CF of which are connected to input terminals IN and IN of a completely differential type operational amplifier circuit during a sample period, by way of reset switches RS and RS connecting the input terminals IN and IN and output terminals OUT and OUT of the completely differential type operational amplifier circuit the common phase feedback hold capacitors CF and CF are charged to thereby determine a balance point of a middle value of differential output signals from the output terminals OUT and OUT and during a hold period, the balance point of the middle value of the differential output signals is maintained by electric charge charged to the common phase feedback hold capacitors CF and CF regardless of the differential output signals.

Sample-and-hold circuit and A/D converter

A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O and I/O of a latch circuit are connected to the drain terminals of MOS transistors M and M having the same characteristics. Input terminals IN and IN are provided to the gate and source terminals of the MOS transistor M and input terminals IN and IN are provided to the gate and source terminals of the MOS transistor M A bias circuit brings the MOS transistors M and M into the same bias state. The difference of the input signals supplied to the input terminals IN and IN is compared with the difference of the input signals supplied to the input terminals IN and IN Since the comparison result is outputted from the first and second input/output terminals I/O and I/O the input offset voltage does not affect the differential comparison circuit. Therefore, the differential comparison circuit can set the reference voltage to the differential signal and can easily obtain required accuracy.

Differential comparison circuit

There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations, an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with. Therefore, the capacity of the AC coupling capacitor can be reduced. Consequently, the circuit scale can be decreased.

Oscillator circuit with reduced capacity for AC coupling capacitor

There is disclosed a MOS transistor output circuit capable of suppressing ringing and other noises and of operating at high speed under low power supply voltages. A signal corresponding to an input signal is applied to the gates of a first p-channel MOS transistor and a first n-channel MOS transistor. A control circuit detects the falling edge of the input signal to create a first signal. A second p-channel MOS transistor is held in conduction by the first signal during a period beginning with the rising edge of the output signal and ending with the instant at which the output signal can be regarded as having logic high (H) level. The rising edge of the input signal is detected to create a second signal. A second n-channel MOS transistor is held in conduction by the second signal during a period beginning with the falling edge of the output signal and ending with the instant at which the output signal can be regarded as having logic low (L) level.

MOS transistor output circuit

There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inveter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption.

Oscillator circuit with current limiting devices

The first amplifier circuit D,is formed by connecting drains of a pair of N-channel MOS transistors forming the first current mirror circuit CM,respectively to the drains of P-channel MOS transistors,and,as a differential input portion, and the second amplifier circuit D,is formed by connecting drains of a pair of P-channel MOS transistors forming the second current mirror circuit CM,respectively to the drains of N-channel MOS transistors,and,as a differential amplifier circuit. The first and second differential amplifier circuits D,and D,can amplify the first and second signals having cycles corresponding with each other with their duty ratios kept unchanged regardless of their operating point potentials. Further, the two outputs are combined into one output to suppress variation of the operating point potential of the output attributable to process-related factors, fluctuation of the power supply potential due to the oscillating operation and the like.

There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with. Therefore, the capacity of the AC coupling capacitor can be reduced. Consequently, the circuit scale can be decreased.

The drains of P- and N-channel MOS transistors 1 and 2 are connected to each other. An output terminal is formed at the node of the drains. Each of first and second amplifier stages 4 and 5 is configured by cascading an n number of CMOS inverters. The amplifier stages drive first and second last-stage CMOS inverters 6 and 7 to drive the P- and N-channel MOS transistors 1 and 2, respectively. A dummy CMOS inverter 8 is disposed so that the input is connected to the node of the second amplifier stage 5 and the second last-stage CMOS inverter 7. The load of the second amplifier stage 5 is equal to that of the first amplifier stage 4. The drivabilities of the CMOS inverters of the same stage in the first and second amplifier stages 4 and 5 are made equal to each other. According to this configuration, the number of CMOS inverters which must be checked in a process of adjusting the duty can be reduced.

Tristate output circuit

An oscillation circuit that improves the duty controllability by cross-coupling ring oscillators that are comprised of current inverters. The sources of current supply circuits 4a-4c and 6a-6c are connected to a power supply and their drains are connected to terminals A in corresponding current inverters, respectively. Each of the gates of those current supply circuits receives an output of a current inverter corresponding, one to one, to a current inverter to which the current supply circuit is connected.

Oscillation circuit

There is disclosed an oscillator circuit comprising the first load capacitor with one electrode there of being connected with an input side of a CMOS inverter within a quartz oscillator circuit, and the second load capacitor with one electrode there of being connected with the output side of the inverter, wherein the inverter is coupled to a lower potential side via a current-limiting device, and the other electrodes of the first and second load capacitors are coupled to a lower potential side via the above-described current-limiting device. Thus, variations in the power-supply voltages synchronized with oscillation are reduced with realization of lower current consumption.

Piezoelectric oscillator circuit

There is disclosed a voltage-controlled oscillator circuit capable of being operated at low power supply voltages and accomplishing low electric power consumption. The circuit permits the duty cycle to be controlled well. The circuit is capable of operating at high speeds. The circuit comprises a first and a second dynamic latch circuits producing oscillation output. Each dynamic latch circuit consists of a series combination of a P-channel MOS transistor and an N-channel MOS transistor. An output terminal is connected to the junction of these two transistors. The output from each latch circuit is inverted according to the voltage at the gate of each MOS transistor and dynamically latches the state of the output. This inversion is performed by turning on the MOS transistors by first and second capacitive elements and by first and second comparator circuits. The capacitive elements are charged and discharged by the outputs from the dynamic latch circuits. Voltages for charging the capacitive elements are applied to the comparator circuits. The switching operation is performed at a higher speed than where a flop-flop is used. Consequently, the oscillation frequency is improved. These MOS transistors do not simultaneously conduct and so electric currents passing through the transistors can be suppressed. Since the timing at which the inversion is made is determined by the charging rates of the capacitive elements, the duty cycle can be controlled well.

Voltage-controlled oscillator circuit

To provide a resistor array circuit device and variable gain device which make possible precise setting of attenuation factors and the like as well as prevention of generation of gridge noise, a resistor array circuit device has resistors R1.sub.1 to R1.sub.n-1, each with a resistance value R, resistors R2.sub.1 to R2.sub.n, each with a resistance value aR, resistor R3 having a resistance value (l+b)R, switches SW.sub.1 to SW.sub.n for switching connection of resistors R2.sub.1 to R2.sub.n to a terminal T3 or a terminal T4, and a control circuit for controlling switches SW.sub.1 to SW.sub.n so that resistors R2.sub.1 to R2.sub.m-1 on a terminal T1 side of an arbitrary resistor R2.sub.m are connected to terminal T4 and resistors R2.sub.m to R2.sub.n on a terminal T2 side of resistor R2.sub.m are connected to terminal T3, the values of the a and b being determined based on b={-1+(1+4a).sup.1/2 }/2 and 1/2&lt;a/(1+a+b). A variable gain device uses the above resistor array circuit device with an operational amplifier Op and a resistor R4.

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Tokyo, Japan

Satoru Miyabe