Fujitsu Corporation

Fujitsu Vlsi Limited

Satoru Mihara

Takeyasu Saito

Naoya Sashida

Kaoru Saigoh

Kenichi Inoue

Yukinobu Hikosaka

Yasutaka Ozaki

Jirou Miura

Tatsuya Yokota

Soichiro Ozawa

Koji Tani

Yoshinori Obata

Shan Sun

Shuzo Fujimura

Katsuyoshi Matsuura

Yoshimasa Horii

Jeffrey Scott Cross

Tatsuya Takeuchi

Keisuke Shinagawa

Mitsushi Fujiki

Takushi Motoyama

Daisuke Komada

Naomichi Abe

Naoyuki Satoh

Naoki Nishida

George Hickert

Masaaki Aoyama

Yasunari Motoki

Toshimasa Kisa

Kunihiko Nagase

Yukari Mihara

Kouji Nozaki

A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

Semiconductor device and method of manufacturing the same

A method for the fabrication of a cap layer on a top electrode layer of a ferroelectric capacitor includes the steps of depositing an amorphous layer, usually made of Sr Ru O , on the top electrode and then annealing the amorphous layer in two stages in order convert the amorphous layer into the cap layer. The first anneal is performed at 500&deg; C. to 700&deg; C. in a non-oxidizing atmosphere, such as nitrogen, and converts the amorphous layer into a crystallized layer of Sr Ru O . The second anneal is performed at 300&deg; C. to 500&deg; C. in an oxidizing atmosphere, such as oxygen, and converts the crystallized layer into the cap layer. The method is applied to the formation of a ferroelectric capacitor element of an integrated semiconductor device.

Process for producing a strontium ruthenium oxide protective layer on a top electrode

A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

There is provided an RF sputtering film forming method of forming a compound film having a stable composition by use of stable plasma with a broad process window to thus facilitate composition control of the compound film. In the RF sputtering film forming method, an alternating voltage or alternating current is applied to a part or all of walls positioned on the outside of a space formed between a wafer and a target, or an electron temperature in the plasma is reduced by oscillating the RF power in a pulse fashion, or a sputtering gas is composed of at least one kind of gases of helium, neon, xenon, and krypton, or a minus voltage is applied to a part or all of the walls positioned on the outside of the space formed between the wafer and the target.

Sputtering film forming method, sputtering film forming equipment, and semiconductor device manufacturing method

A carbon-containing film, which is made of a carbon-containing material, is adhered to the inner wall of a chamber. A semiconductor substrate is arranged in the chamber whose inner wall has the carbon-containing film adhered thereto. A plasma of a process gas which contains a rare gas is generated in the chamber, and such an electric field as to cause ions contained in the plasma to be attracted to a surface of the semiconductor substrate is applied in order to etch a part of the surface layer of the semiconductor substrate. During the etching, a film which contains a constituent or constituents of an etched film adheres to the surface of the carbon-containing film. The carbon-containing film prevents the peeling off of such an adhering film from the inner wall of the chamber, thereby reducing the generation of particles.

Semiconductor device manufacturing method including plasma etching step

Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.

Semiconductor device manufacturing method including ashing process

In a method of manufacturing a semiconductor device, a first film essentially consisting of silicon is deposited on the surface of a semiconductor substrate. A second film essentially consisting of material having a proper etching selection ratio relative to tungsten is deposited on the first film. A third film essentially consisting of tungsten is deposited on the second film. A resist pattern is formed on the third film. The third film is etched and patterned to the surface of the second film, by using the resist pattern as a mask. The second film is etched to have the same shape as the third film. The first film is etched to have the same shape as the third film. After the step of patterning the third film and before the step of patterning the first film, the resist pattern is heated to a temperature of 80.degree. C. or higher, the semiconductor substrate is exposed in atmospheric air, and the resist pattern is removed.

Method of manufacturing semiconductor device with patterned lamination

A method for performing plasma downstream processing by generating plasma of an oxygen-containing gas with a microwave in a space having a thickness of 1/10, or less, of a wavelength .lambda. of the microwave, deriving the generated plasma of the oxygen containing gas from such space through an opening formed around the central portion of such plasma generating space through a gap having a loop-shaped cross section in a plane parallel to the space and folded cross section in a plane including a central portion normal to such space; and irradiating the generated plasma of the oxygen containing gas derived from the plasma generating space to an object to be processed.

Method for plasma downstream processing

A method of manufacturing a semiconductor device including the steps of: forming an insulating film on a silicon substrate; forming a resist pattern on the insulating film; etching the insulating film by using the resist pattern as an etching mask to expose a surface of the silicon substrate; and ashing the resist pattern and etching a surface layer at the exposed surface of the silicon substrate at the same time. The ashing/etching step may be performed first at a high temperature at or above 40.degree. C. and then at a lower temperature.

Manufacture of semiconductor device with ashing and etching

An apparatus for performing plasma downstream processing comprises: a microwave introduction chamber defined by a wall having a microwave transmitting window formed of a microwave transmissive material at a part thereof; a plasma generating chamber facing to said microwave introduction chamber through said microwave transmitting window and having a conductive microwave shield disposed generally parallel to said microwave transmitting window, to define a plasma generating space, said microwave shield including a central member which is formed of a continuous conductor and an outer member disposed outside the central member through a gap which has a folded cross sectional shape in a plane including a central normal to the microwave transmitting window; and an evacuatable processing chamber disposed adjacent to said plasma generating chamber through said microwave shield. The gap formed between the central member and the outer member can have a large cross section compared to the conventional through holes in the punching metal. Folded configuration of the gap can prevent direct passing-through of charged particles through microwave shield. A reliable and fast ashing process can be realized.

Plasma downstream processing

A method for ashing a resist on a wafer in a plasma reaction chamber comprises the steps of flowing a non-activated oxygen containing gas into the plasma reaction chamber immediately before loading the wafer to the plasma reaction chamber, and then carrying out a plasma ashing of the resist. In one of the preferred embodiments, after the reaction chamber was exposed to the atmosphere and then evacuated to vacuum, a mixed gas of oxygen (90% in volume) and water vapor (10% in volume) was flown into the reaction chamber with 1000 seem and 1 Torr for 5 min. and subsequently the ashing was carried out. The method prevents the ashing rate from decreasing with ashing time.

Plasma ashing method with oxygen pretreatment

A process for forming a resist mask pattern includes the steps of forming a resist layer of organic material in a multilevel resist process on a layer to be etched, and selectively etching a planarizing lower layer used in the resist layer by using an etching gas of oxygen under a plasma condition, in which a compound gas of at least one element selected from the group consisting of B, Si, Ti, Al, Mo, W and S is added to the etching gas. For example, the compound gas comprises BCl.sub.3, BH.sub.3, TiCl.sub.4, S.sub.2 Cl.sub.2, SiCl.sub.4 or the like. During the etching, a compound oxide, e.g., B.sub.2 O.sub.3, SiO.sub.2 or the like, is deposited on sidewalls of the lower layer to form a protective layer which prevents undercutting.

Process for forming resist mask pattern

A trench etching process comprises the steps of: preparing a substrate, forming a mask pattern for the trench etching having a material different from that of the substrate, on the substrate, and detecting changes in results of emission spectroanalyses generated by etching the mask pattern and the substrate while using the etching ratios of the mask pattern and the silicon substrate to determine that the trench etching is completed.

Trench etching process

A downstream microwave plasma processing apparatus useful in fabricating an integrated circuit semiconductor device includes a waveguide, a microwave transmitting window perpendicular to a microwave electric field in the waveguide, a plasma generating chamber below the window and a reaction chamber separated from the plasma generating region by a gas-porous microwave shield. The microwave energy is transmitted into the plasma generating chamber through the microwave transmitting window, and generates a plasma which is confined therein by the shield. Radicals of a short-lived reactive gas, generated in the plasma, pass through the shield and impinge onto a workpiece placed in the reaction chamber. Uniform and effective downstream plasma etching or ashing is produced.

Growing community of inventors

Kawasaki, Japan

Satoru Mihara