Murata Manufacturing Co., Ltd.

Satoru Matsuyama

Satoshi Matsumura

Kazuhiro Nakamuta

Toshiki Matsumura

Yuji Shintomi

A data communication device includes: a fixed value memory that stores a fixed value; a received data memory that stores received data inputted through a bus; an output data memory that stores output data; a comparison determination unit that outputs a comparison determination result signal indicating a determination result of comparing the fixed value and a value of the received data; a data output unit that has a first state of outputting the output data to the bus and a second state of not outputting the output data to the bus; a command analyzing unit that outputs a data output control signal based on a command; and an output controller that outputs a control signal for controlling the data output unit to enter the first state or the second state based on the comparison determination result signal and the data output control signal.

Data communication device and data communication module

A digital output monitor circuit includes a first digital circuit that performs mutual conversion between serial data and parallel data, a second digital circuit that decodes data output from the first digital circuit and generates a control signal for an analog circuit, and a third digital circuit that converts at least the control signal for an analog circuit into digital data. The first digital circuit converts the data output from the third digital circuit into serial data and outputs as an output data signal.

Digital output monitor circuit and high frequency front-end circuit

A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.

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Kyoto, Japan

Satoru Matsuyama