Fujitsu Corporation

Fujitsu Vlsi Limited

Kyushu Fujitsu Electronics Limited

Satoru Masaki

Shinya Udo

Fumitaka Asami

Fusao Seki

Akinori Yamamoto

Kazuo Ohno

Masao Imai

A first level converter is provided with an input transistor circuit and an output transistor circuit. The input transistor circuit is supplied with power from a first power source and outputs a complementary signal on the basis of an input signal. The output transistor circuit is supplied with power from a second power source, and amplifies and outputs the complementary signal. A second level converter is provided with a pulse generating circuit and a signal output circuit. The pulse generating circuit is supplied with power from the first driving power source, and generates a one-shot pulse signal. The signal output circuit is supplied with power from the second driving power source, latches the one-shot pulse signal and outputs the signal. The semiconductor integrated circuit is provided with a first circuit system, a level conversion circuit and a second circuit system. The first circuit system is driven by being supplied with power from the first driving power source. The level conversion circuit is supplied with power from the first driving power source, and converts an output signal of the first circuit system into an input signal of the second circuit system. The second circuit system drives a signal with level converted by being supplied with power from the second driving power source. Further, in the semiconductor integrated circuit, a bidirectional level conversion circuit and a signal control means are provided, and the first and the second driving power sources are wired in a lattice form in a semiconductor chip.

Level converter for CMOS 3V to from 5V

A semiconductor integrated circuit device includes an internal logic circuit which is reset in response to a reset signal, and an abnormal voltage detection circuit, operatively connected to said internal logic circuit and an external terminal, for generating the reset signal when an abnormal voltage is detected at the external terminal.

Integrated circuit device having high abnormal voltage detection circuit

A circuit for reading out address data applied to a memory in a one-chip microcomputer which does not have any address terminals but has input/output terminals. The circuit comprises a program counter for specifying reading out addresses of the memory. Transfer gates and a shift register are also provided. The transfer gates transfer the contents of the program counter to the shift register when an address output enable signal is applied to the transfer gates. The contents stored in the shift register are read out to an address output terminal connected to the shift register.

Circuit for reading out address data applied to a memory in a one-chip

Growing community of inventors

Kawasaki, Japan

Satoru Masaki