Renesas Technology Corp.

Renesas Esatern Japan Semiconductor, Inc.

Satoru Konishi

Hirokazu Nakajima

Tsuneo Endoh

Masaaki Tsuchiya

Kazumasa Yanagisawa

Yasunari Umemoto

Atsushi Kurokawa

Mitsuaki Katagiri

Yoshinori Imamura

Akira Muto

Satoshi Sasaki

Yu Hasegawa

Yuji Shirai

Tomio Yamada

Chushiro Kusano

Yasuo Osone

Kenya Kawano

Chiko Yorita

Tsutomu Ida

Seiichi Tomoi

Mamoru Ito

Tsuneo Endou

Tsuneo Endo

Kazuaki Uehara

Koji Odaira

A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.

Semiconductor device

A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Semiconductor device and manufacturing method therefor

The present invention realizes strengthening of a ground of a lower-surface ground electrode of an upper semiconductor chip and miniaturization in a semiconductor module on which two semiconductor chips are mounted in a stacked manner. A lower semiconductor chip is fixed to a bottom of a recess formed in an upper surface of a module board, and an upper semiconductor chip is fixed to an upper surface of a support body made of conductor which is formed over the upper surface of the module board around the recess. External electrode terminals and a heat radiation pad are formed over a lower surface of the module board.

Semiconductor module

The present invention realizes the miniaturization of a semiconductor module. The semiconductor module includes a module board having external electrode terminals and a heat radiation pad over a lower surface thereof, a first semiconductor chip incorporating an initial-stage transistor of a high frequency power amplifying device therein, a second semiconductor chip incorporating a next-stage transistor and a final-stage transistor therein, and an integrated passive device which constitutes a matching circuit. At least one of the first semiconductor chip and the second semiconductor chip and the integrated passive device are mounted over an upper surface of the module board in an overlapped manner.

Power amplifier module

There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.

Semiconductor device and manufacturing the same

The size of a power amplifier module is reduced. The power amplifier module includes a module substrate, a lower chip flip-connected to the module substrate, an upper chip stacked face up onto the lower chip, a common electrode disposed on a back surface of the upper chip, plural wires for connecting the upper chip and the module substrate with each other, plural wires for connecting the common electrode and the module substrate with each other, plural chip parts mounted on the module substrate, and a sealing portion formed on the main surface of the module substrate. The common electrode is connected to the module substrate through wires to strengthen the GND of the upper chip. Since the lower chip is flip-connected to the module substrate, the difference in size between the upper and lower chips is diminished to attain a reduction in size of the power amplifier module.

A semiconductor integrated circuit device has a semiconductor substrate with a plurality of pads disposed over a main surface of the substrate along one side thereof. A plurality of input/output cells are disposed corresponding to the plural pads over the main surface of the substrate. An internal circuit forming section is disposed over the main surface of the substrate. Power supply wirings for the internal circuit supply potentials to the internal circuit forming section. The plural input/output cells include signal cells and power supply cells for internal circuit respectively. Signal pads are disposed corresponding to the signal cells and electrically connected the signal cells. Power supply pads for the internal circuit are respectively disposed corresponding to the power supply cells and electrically connected to the power supply cells and the power supply wirings.

Semiconductor integrated circuit device

Growing community of inventors

Saku, Japan

Satoru Konishi