Fujitsu Corporation

Spansion Llc.

Fujitsu Microelectronics Limited

Fujitsu Vlsi Limited

Fujitsu Semiconductor Limited

Satoru Kawamoto

Yoshiharu Kato

Hajime Sato

Takaaki Furuyama

Kazufumi Komura

Kenji Shibata

Yasushige Ogawa

Yuji Nakagawa

Shozo Kawabata

Kenta Kato

Kenji Nagai

Shinji Nagai

Motoki Mizutani

Masao Nakano

Hideki Arakawa

Akira Takashima

Kotoku Sato

Fumihiko Taniguchi

Tetsuya Hiraoka

Shinichiro Ikeda

Syuichi Saito

Makoto Niimi

Yoshichika Nakaya

Akihiko Watanabe

Norikatsu Suzuki

Hideho Taoka

Yoshihiro Suzumura

Kanji Hirano

A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.

Method and apparatus for address allotting and verification in a semiconductor device

A storage device and its control method are described, according to which a bias voltage to be supplied to a memory cell array is selected from boosted voltages which are increased from an external voltage and non-boosted voltages which are not increased from the external voltage. In the period during which a DC-DC converter section supplies a boosted voltage increased from the external voltage to an internal bias line for supplying a bias voltage to the memory cell array, a non-boosted voltage supply section for supplying a non-boosted voltage equal to or less than the external voltage is in its inactive state. In the period during which the non-boosted voltage supply section supplies a non-boosted voltage to the internal bias line, the DC-DC converter section is in its inactive state. In the period during which a boosted voltage is supplied to the internal bias line, the DC-DC converter section is used for ensuring sufficient power supply ability, and in the period during which the non-boosted voltage is supplied to the internal bias line, the DC-DC converter section can be kept in its inactive state. Thus, the power consumed by the DC-DC converter section can be saved in the period during which the supply of a boosted voltage is unnecessary.

Storage device and control method thereof

A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.

Semiconductor memory device and refresh method for the same

A semiconductor device () is provided which includes a regular cell array unit (), a redundant cell array unit () that is provided in relation to the regular cell array unit (), and a PGM/ER state machine () that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S) into the redundant cell array unit (). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.

Semiconductor device and program data redundancy method therefor

It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k&#x2212;1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

Semiconductor memory device and method of controlling the semiconductor memory device

There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value. Thereby, transient state of an oscillation-frequency control signal (VR) can be detected. That is, there can be avoided an output of an unstable oscillation signal due to a transient oscillation-frequency control signal (VR).

Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit

A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

Voltage detection circuit, semiconductor device, method for controlling voltage detection circuit

A memory system (A) includes a memory section (A) and a memory control section (A). The memory section (A) includes a test circuit (A), a data register (A), a data output section (A), and a memory core section (A). Data DI is held in the data resistor (A). The test circuit (A) outputs write inhibit signal WINH to the memory core section (A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (A) and select signal S are inverted and, in response thereto, retained data DR of the data register (A) is outputted as output data DO from the data output section (A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.

Memory system and test method therefor

During an erasing sequence, after a preprogram operation (S), an erasing operation (S), and an APDE operation (S) are executed and confirmation by an APDE verify operation (S: P) and confirmation by an erase-verify operation (S: P) are completed, step A is executed prior to a soft-program operation (S) of a plurality of memory cells. A dummy memory cell program operation (S) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S) can be prevented, and excessive soft-programming can be avoided.

Non-volatile memory device and erasing method therefor

A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k&#x2212;1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.

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Kasugai, Japan

Satoru Kawamoto