Mitsubishi Denki Kabushiki Kaisha

Satoru Kamoto

Kiyoto Watabe

Masahiko Yoshimoto

Kenji Anami

A method of fabricating a MOS field effect semiconductor device having an LDD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by anisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

Method of fabrication LDD semiconductor device with amorphous regions

A method of fabricating a MOS field effect semiconductor device having an LLD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by anisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

Method of fabricating semiconductor device

A power supply voltage to be applied to a metallic connection 36a is supplied through an n.sup.+ diffusion region 34a, an N type well 22, an n.sup.+ diffusion region 34c and a metallic connection 36C to a p.sup.+ diffusion region 23b serving as a power supply line. An n.sup.+ diffusion region 73 serving as a ground line is grounded through a metallic connection 76c, a p.sup.+ diffusion region 74c, a P type well 72, a p.sup.+ diffusion region 74b and a metallic connection 76b.

Complementary metal oxide semiconductor integrated circuit with unequal

A method of fabricating a MOS field effect semiconductor device having an LDD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by unisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.

An electrified fluid flows through a main pipe and its bypass line including a conducting pipe insulated from the remaining pipes and the main pipe. While the electrified fluid flows through the insulating pipe the latter acquires all electric charges which is, in turn, measured, as a current, by an ammeter connected between the insulated pipe and ground. A flow meter is disposed in the bypass line on the outgoing side of the insulated pipe and measures a flow rate. An electric charge density is calculated from the measured current and flow rate.

Growing community of inventors

Hyogo, Japan

Satoru Kamoto