Panasonic Corporation

Satoru Itou

Hiromasa Fujimoto

Toshie Kutsunai

Susumu Akamatsu

Yoshiya Moriyama

Hiroshi Ohkawa

A semiconductor device has a first MIS transistor. The first MIS transistor includes a first source/drain region of a first conductivity type which includes a silicon compound layer causing a first stress in a gate length direction of a channel region in a first active region, and a stress insulating film which is formed on the first active region to cover a first gate electrode, a first sidewall, and the first source/drain region, and which causes a second stress opposite to the first stress. An uppermost surface of the silicon compound layer is located higher than a surface of a semiconductor substrate located directly under the first gate electrode. A first stress-relief film is formed in a space between the silicon compound layer and the first sidewall.

Semiconductor device

A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount dfrom the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1&#x3c;0.5s.

A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.

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Hyogo, Japan

Satoru Itou