Kabushiki Kaisha Toshiba

Satoru Hoshi

Masami Masuda

Kazuhiko Takahashi

Yasumitsu Nozawa

Takayuki Kawaguchi

Takayuki Otani

Tadashi Someya

A semiconductor memory device includes normal row selection lines (NWL1 to NWL128) for selecting one of normal rows, a spare row selection line (SWL) for selecting a spare row instead when one of the normal rows has a defect, fuses (F1 to F128) which are respectively arranged on the normal row selection lines, and blown when a defect exists, a normal row non-selection circuit (inverters IN3 and IN6 and gate G3) when one of the fuses (F1 to F128) is blown, setting a corresponding normal row in a non-selected state, and a spare row selection circuit (gates G4, G5, and G6, transistors P2 and N1, a NOR gate NR1, and an inverter IN6) selecting the spare row instead of the defective normal row. The spare row selection circuit performs dynamic operation in synchronism with a clock (ck). In this manner, control of, when a defect exists in a normal row or column, switching the defective row or column to a spare row or column is performed by dynamic operation in synchronism with an internal clock, thereby increasing the access speed.

Semiconductor memory device

In an asynchronous type memory device for controlling a plurality of bytes independently, even if the byte control signal changes in the write cycle, the automatic power-down can be released and further the data can be read after data have been written. When data are transferred from the input/output terminals I/OUBm and I/OLBn to the internal data buses DbusUB and DbusLB through the upper byte data input buffers DinUBm and the lower byte input buffers DinLBn, the change detecting sections UWTD and LWTD generate the write start synchronous pulse .phi.BWS and the write end synchronous pulse .phi.BWE on the basis of the logical result of the write request signal /WE and the control signal /UB or /LB. Therefore, when the data are written and read for each byte independently, data can be written in and read from the memory cells irrespective of the data conditions. Further, the written data can be read immediately without changing the addresses.

A plurality of voltage supply circuits each including an inverter circuit are provided at the final stage of a row decoder. The voltage supply circuits are supplied with voltage Vdd and voltage Vxx. The voltage Vxx is set at a level of Vss in a normal operation mode and at a level higher than that of Vdd in a burn-in test mode. In the latter mode, the voltage Vdd is applied to the voltage supply circuit connected to a selected word line, while the voltage Vxx (higher than Vdd) is applied to the voltage supply circuit connected to a nonselected word line. All word lines are therefore set at a high level and rendered in a selective state.

Semiconductor memory device having a test circuit

In a CMOS type static RAM, a substrate bias voltage VPP higher than a power supply voltage supplied from an outer unit is supplied to an N type substrate region of a PMOS transistor of a CMOS inverter forming a word line driving circuit to bias the N type substrate region to the bias voltage VPP and to a power supply terminal of the CMOS inverter as a power supply voltage. Whereby, resistance of storage data to incidence of radioactive rays is increased just after writing to a storage node of a memory cell is ended, and a soft error generation rate can be easily reduced.

Semiconductor memory device with a substrate bias voltage generation

A semiconductor memory device including: a memory cell array having at least one cell array unit, the cell array unit including a plurality of memory cells; a decoder for selecting at least one the memory cell in accordance with an externally supplied address; an input/output terminal for outputting data read from the selected memory cell and for receiving data supplied externally and sending the data to the selected memory cell; at least one data line for connecting the input/output terminal to each the cell array unit; sense amplifiers serially connected to each the data line in a multiple stage configuration for amplifying the read data; a write buffer connected in parallel with one of the sense amplifiers connected to each data line; by-pass switching elements connected between input and output terminals of the other sense amplifiers connected to each the data line; and a control circuit for applying an on-signal to at least one by-pass switching element when writing data, the on-signal turning on at least one by-pass switching element.

In a data read circuit, for a semiconductor storage device, data of a memory cell (11) selected according to an address is inputted to a sense amplifier (22) via a pair of complementary first data lines (N1 to N6). The sense amplifier outputs the inputted and amplified data to a pair of complementary second data lines (N7, N8). First switching means (Tr3) equalizes the pair of complementary first data lines (N5, N6) at the input side of the sense amplifier (22) by making the first data lines conductive with respect to each other. Second switching means (Tr4) equalizes the pair of complementary second data lines (N7, N8) by making the second data lines conductive with respect to each other. Third switching means (Tr5, Tr6) equalizes by making the pair of first data lines (N5, N6) at the input side of the sense amplifier (22) and corresponding ones of the pair of second data lines (N7, N8) conductive with respect to each other. Second equalizing pulse generator means (42) generates a second equalizing pulse (.PHI..sub.eq ') when the address is changed, and turns on the first switch means (Tr3) by applying the second equalizing pulse to a control terminal of the first switch means. First equalizing pulse generator means (41) generates a first equalizing pulse (.PHI..sub.eq) when the address is changed, and turns on the second and third switching means (Tr4, Tr5, Tr6) by applying the second equalizing pulse to gate terminals of the second and third switching means. The load capacitance ]C(.PHI..sub.eq ')] connected to an output terminal of the second equalizing pulse generating means (42) is set smaller than the load capacitance [C(.PHI..sub.eq)] connected to an output terminal of the first equalizing pulse generator means (41). The number of stages of logical circuits constituting the second equalizing pulse generator means (42) is smaller than the number of stages of logical circuits constituting the first equalizing pulse generator means (41). Accordingly, with this data read circuit for a semiconductor storage device, the second equalizing pulse (.PHI..sub.eq ') from the second equalizing pulse generator means (42) is established earlier than the first equalizing pulse (.PHI..sub.eq) from the first equalizing pulse generator means (41).

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Kawasaki, Japan

Satoru Hoshi