Hitachi, Ltd.

Elpida Memory, Inc.

Renesas Electronics Corporation

Other

Texas Instruments Corporation

Mitsubishi Denki Kabushiki Kaisha

Satoru Hanzawa

Takeshi Sakata

Motoyasu Terao

Hideyuki Matsuoka

Yoshitaka Sasago

Kazuhiko Kajigaya

Riichiro Takemura

Tomonori Sekiguchi

Hitoshi Kume

Norikatsu Takaura

Masaharu Kinoshita

Kiyoo Itoh

Nozomu Matsuzaki

Satoru Akiyama

Akio Shima

Takashi Kobayashi

Osamu Nagashima

Kenzo Kurotsuchi

Toshihiro Tanaka

Fumihiko Nitta

Hiroyuki Minemura

Katsuro Watanabe

Kenchi Ito

Makoto Saen

Sadayuki Morita

Takahiro Morikawa

Takahiro Sonoda

Haruko Tadokoro

Hiroshi Ichikawa

Koichiro Ishibashi

Hiroyuki Mizuno

Katsutaka Kimura

Toshiyuki Mine

Seiji Miura

Masayuki Miyazaki

Masaru Kokubo

Akira Kotabe

Hirokazu Aoki

Yoshikazu Iida

Minoru Ogushi

Kiyoshi Hasegawa

Tsukasa Ooishi

Takao Watanabe

Daisuke Suzuki

Shinichiro Kimura

Toshimichi Shintani

Yoshihisa Fujisaki

Naoki Kitai

Nobuhiro Shiramizu

Junji Shigeta

Kiyoshi Nakatsuka

Norikastsu Takaura

A computer system supplies a health service using body information measured by a measurement instrument. The computer system includes a computer that includes an analysis unit analyzing memory of a user. The analysis unit analyzes an error pattern based on a history of a matching-determination process for body information transmitted by the measurement instrument and body information input by the user, calculates a first evaluation value for evaluating a cognitive function based on an analysis result of the error pattern, analyzes an action pattern related to an input action of body information of the user, calculates a second evaluation value for evaluating the cognitive function based on an analysis result of the action pattern, and evaluates the cognitive function of the user based on the first evaluation value and the second evaluation value.

Computer system, cognitive function evaluation method, and program

An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG.).

Semiconductor storage device

Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line () which is provided above the substrate; a first laminated body, which is disposed above the first word line (), and which has the N+1 (N&#x2267;1) number of first inter-gate insulating layers (-) and the N number of first semiconductor layers (-) alternately laminated in the height direction of the substrate; a first bit line (), which extends in the direction that intersects the first word line (), and which is disposed above the laminated body; a first gate insulating layer () which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (-) and those of the N number of the first semiconductor layers (-); a first channel layer () which is provided on the side surface of the first gate insulating layer (); and a first variable resistance material layer () which is provided on the side surface of the first channel layer. The first variable material layer () is in a region where the first word line () and the first bit line () intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

Semiconductor storage device and method for manufacturing same

The invention is provided to suppress a current supplied to a storage element so as not to vary for each layer in a semiconductor memory device obtained by connecting a plurality of memory cells in series. A semiconductor memory device according to the invention includes a plurality of memory cells connected in series between a first signal line and a second signal line, and supplies a different gate voltage to at least two of selection transistors included in the memory cells, respectively (refer to FIG.).

Series connected resistance change memory device

In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Semiconductor device and its manufacturing method

A semiconductor storage apparatus provides a large capacity phase-change memory possessing high speed operation, low electrical current, and high-reliability. During the period that a read-out start signal is activated in the memory region control circuit and the block of pairs of sense-latch and write driver is performing the verify read in the upper section memory region; the write enable signals in the memory region control circuit are activated and the block of pairs of sense-latch and write driver perform rewrite operation of the data in the lower section memory region. This type of operation allows cancelling out the time required for the verify read and the time required for the time-division write operation by performing the verify read in one memory region, while performing time-division rewrite in other memory region, to achieve both higher reliability rewrite operation along with suppressing the rewrite operation peak electrical current.

Semiconductor storage apparatus or semiconductor memory module

Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.

The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line () and a bit line () and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.

A high-speed large-capacity phase-change memory is achieved. A semiconductor device according to the present invention includes: a plurality of memory planes MP; a plurality of storage information register groups SDRBK paired with the plurality of memory planes; and a chip control circuit CPCTL. The plurality of memory planes include a plurality of memory cells. Also, the plurality of storage information register groups temporarily retain information to be stored in the plurality of memory planes. Further, the chip control circuit includes a register which temporarily stores a value indicating volume of the storage information, and a first storage information volume is smaller than a second storage information volume. When the first storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a first period. When the second storage information volume is written, the plurality of memory planes and the plurality of storage information register groups are activated during a second period. By such a structure, the first period is shorter than the second period.

Semiconductor device

In a phase change memory, when M bit (8 bits=1 byte) data is written, erase operation and program operation are performed in units of n bit (M&#x3e;n) data. Further, when M bit data is written, program operation is performed in units of the n bit (M&#x3e;n) data. Further, when M bit data is read from the memory cell, read operation is performed in units of the n bit (M&#x3e;n) data. For example, when the data is written into to the phase change memory, the data is not overwritten but program is performed after once erasing the target memory cell. The data size for erasure and the data size for program are made equal. Erase and program operation are performed only for the demanded data size.

Semiconductor device and data processing system

A semiconductor device has multiple memory cell groups arranged at intersections between multiple word lines and multiple bit lines intersecting the word lines. The memory cell groups each have first and second memory cells connected in series. Each of the first and the second memory cells has a select transistor and a resistive storage device connected in parallel. The gate electrode of the select transistor in the first memory cell is connected with a first gate line, and the gate electrode of the select transistor in the second memory cell is connected to a second gate line. A first circuit block for driving the word lines (word driver group WDBK) is arranged between a second circuit block for driving the first and second gate lines (phase-change-type chain cell control circuit PCCCTL) and multiple memory cell groups (memory cell array MA).

Adverse effects of a parasitic resistance and a parasitic capacitance of a driver circuit to a memory cell causes problems of thermal disturbance to a not-selected cell, unevenness of application voltage, degradation of a memory element in reading. A capacitor (C) is provided above or beneath a memory cell (MC) that includes a memory element to which a current write memory information and a selection element connected to the memory element. A charge stored in this capacitor writes to the memory element.

Semiconductor memory device

A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a semiconductor layer to which the first current was applied.

Semiconductor storage device with memory cell utilized as a set-dedicated memory cell

Growing community of inventors

Hachioji, Japan

Satoru Hanzawa