Hitachi, Ltd.

Elpida Memory, Inc.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Engineering Co., Ltd.

Hitachi Ulsi Engineering Corp.

Satoru Haga

Shuji Ikeda

Hideyuki Matsuoka

Masahiro Moniwa

Keiichi Yoshizumi

Kazuo Nakazato

Hiroshi Kujirai

Tsuyoshi Tabata

Teruo Kisu, Legal Representative

Haruko Kisu, Legal Representative

Naotaka Hashimoto

Yutaka Hoshino

Yasuko Yoshida

Kazushi Fukuda

Kyoichiro Asayama

Takeshi Fukazawa

Eri Okamoto

Yuuki Koide

Kiichi Makuta

A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film () constituting the channel forming region from an n type poly-crystalline silicon film () constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (); and reducing an effective impurity concentration in the poly-crystalline silicon film ().

Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device

A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.

Method of manufacturing semiconductor device having a plurality of trench-type data storage capacitors

When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.

Process for producing semiconductor integrated circuit

An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.

Semiconductor integrated circuit device

Growing community of inventors

Akishima, Japan

Satoru Haga