Fujitsu Corporation

Nippon Telegraph and Telephone Corporation

Satomi Ikeda

Kazuyuki Tajima

Masaaki Kawai

Yuji Takizawa

Hidetoshi Naito

Haruo Yamashita

Hideo Tatsuno

Masayoshi Sekido

A transmission circuit transmits a normal cell data and an idle cell data via a communication line. The idle cell data is transmitted to fill time slots in the communication line at which there is no normal data to be transmitted, each of the normal cell data and idle cell data including first data, second data and third data. The first, second and third data of the normal cell data respectively indicate a destination, an error correcting code of the first data and desired information. The first and second data of the idle cell data have predetermined bit patterns and the third data of the idle cell data may have any arbitrary bit pattern. The transmission circuit includes a first output circuit for outputting the normal cell data, an error correcting code generator for generating the second data based on the first data of the normal cell data supplied from the first output circuit, a second output circuit for outputting the first and second data of the idle cell data, a scrambler for scrambling the third data of the normal cell data supplied from the first output circuit, and a selector for selecting one of the first output circuit, the error correcting code generator, the second output circuit and the scrambler in accordance with a predetermined order, so that the normal cell data and the idle cell data are output from the selector.

Transmission circuit for transmitting fixed-length data

A 1-bit error correction circuit based on CRC calculation is provided with a syndrome generation circuit which determines input parallel data of m bits and which have been converted from n number of m-bit serial data. A 1-bit error detection circuit cyclically supplies a syndrome to a remainder calculation circuit and decodes remainder data obtained from this cyclic supply and detects 1-bit errors. A actual data reproduction circuit calculates the exclusive OR of output data of a predetermined register of a 1'st.about.n'th register of a syndrome generation circuit and data supplied to a predetermined register and obtains parallel data which is the actual data. A correction circuit which calculates a exclusive OR of parallel data obtained from a actual data reproduction circuit and 1-bit error data detected by the 1-bit error detection circuit and outputs corrected data.

One bit error correction method having actual data reproduction function

Growing community of inventors

Kawasaki, Japan

Satomi Ikeda