Tokyo Electron Limited

Tohoku University

Iwatani Corporation

Satohiko Hoshino

Tadahiro Ishizaka

Shigeru Mizuno

Masaru Sasaki

Kaoru Maekawa

Yasushi Mizusawa

Keizo Hirose

Frank M Cerio, Jr

Nobutaka Mizutani

Masahito Sugiura

Mitsumasa Koyanagi

Toshiaki Hongoh

Masaki Narushima

Yusaku Kashiwagi

Hiroyuki Nagai

Hidefumi Matsui

Yuki Chiba

Takafumi Fukushima

Fitrianto

Shinji Ide

Kangwook Lee

Kuzuhiro Hamamoto

Shinya Kikuta

Isao Tsukagoshi

Federica Allegretti

A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

Method for aligning chip components relative to substrate by using liquid

An imprinting method is capable of separating a molding material and a target material rapidly in pattern formation. The imprinting method includes a transferring process for transferring an inverted pattern of a moldhaving a desired pattern formed thereon to a resistby pressing the moldagainst the resist; a curing process for curing the resistby heating or irradiating light; and a separating process for separating the moldfrom the resistafter the resistis cured through the transferring process. The separating process includes a pulling process for pulling the moldaway from the resistin a direction opposite to a direction in which the resistis pressed; and a pushing process for pushing the resistin the same direction as a direction in which the moldpresses the resist

Imprinting method

In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.

Substrate wiring method and semiconductor manufacturing device

An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.

Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication

A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Selective deposition of metal-containing cap layers for semiconductor devices

The present invention relates to a method of lowering dielectric constant of an insulating film including Si, O and CH formed by a chemical vapor deposition process. A process gas containing hydrogen atoms is supplied into a reaction vessel. A microwave is introduced into the reaction vessel to supply a uniform electromagnetic wave, thereby a plasma containing a hydrogen radical is generated in the reaction vessel. The structure of the insulating film is modified by the hydrogen radical contained in the plasma irradiated to the insulating film, lowering the dielectric constant of the film. The microwave is supplied into the reaction vessel through a radial-slot antenna.

Fabrication of low dielectric constant insulating film

In a method for forming an insulating film, a film containing an organic curable material and provided on a substrate for an electronic device is irradiated with an energy plasma produced by a microwave irradiation through a planar antenna member having a plurality of slits to thereby cure the film containing the organic curable material and form the insulating film having a dielectric constant of 3 or less.

Method and apparatus for forming insulating layer

A porous low-k film, a sacrificial film that can be dissolved in a pure water, an antireflection film and a resist film are successively formed on a dielectric film on a wafer and subsequently exposing the resist film to light in a prescribed pattern and developing the resist film so as to form a prescribed circuit pattern in the resist film. Then, the wafer W is etched so as to form a via hole in the porous low-k film, followed by processing the wafer with a hydrogen peroxide solution so as to denature the resist film. Further, the sacrificial film is dissolved in a pure water so as to strip the resist film and the antireflection film from the water. As a result, a via hole excellent in the accuracy of the shape is formed without doing damage to the dielectric film.

Method of manufacturing trench structure for device

A method of fabricating a semiconductor device includes the steps of forming a first insulation film on a substrate by a spin-on process, applying a curing process to the first insulation film at a temperature of 380-500&#xb0; C. over a duration of 5-180 seconds, and forming a second insulation film on the first insulation film by a spin-on process.

Fabrication process of a semiconductor device

Growing community of inventors

Nirasaki, Japan

Satohiko Hoshino