Lsi Logic Corporation

Satish Venugopal

Daniel R Watkins

Venkat Mattela

Gagan V Gupta

Kosala Abeywickrema

Kumar Bhattaram

The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design. The present invention describes the method and apparatus to reverse-synthesize gate netlist level definitions into RTL definitions by parsing and analyzing the gate netlist level definition, generating an equivalent RTL definition, and verifying correctness of the RTL definition.

Gate netlist to register transfer level conversion tool

A random verification environment for verifying a semiconductor device includes a hardware engine programmed to include a random input generator that builds a set of test vectors. A first memory connected between the hardware engine and the semiconductor device stores the set of test vectors and supplies the set of vectors to the semiconductor device under the control of a first state machine generated by the hardware device. A second memory connected to the semiconductor device receives output signals from the semiconductor device in response to input test vectors. A random test iterator in the hardware engine provides a first state machine and also provides a second state machine that writes the signals output from the semiconductor device to the second memory. The test vectors are input to the semiconductor device at a rate equal to the operating rate of the semiconductor device. An expected output generator is arranged to receive the test vectors from the first memory. An output comparator is arranged to receive outputs from the expected output generator and from the second memory and to record whether the output of the semiconductor device for each test vector is the expected output provided by the expected output generator.

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Santa Clara, CA, United States of America

Satish Venugopal