Cadence Design Systems, Inc.

Synopsys, Inc.

Satish Raj

Jeffrey Scott Salowe

David Dah-Juh Chyan

Karun Sharma

Yinnie Lee

Olivier Pribetich

Supriya Ananthram

Gary Matsunami

Dwight D Hill

Sachin Shrivastava

Mark Edward Rossman

David Chyan

Joyjeet Bose

Ying-Hui Wang

Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.

Generating and inserting metal and metal etch shapes in a layout to correct design rule errors

Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.

Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs

One aspect checks and prepares design data () based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation () is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation () may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques

Disclosed are methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect tessellates an area on a layer of an electronic design that is subject to one or more track pattern requirements and dynamically maintains the tessellation structure from the tessellation process for early stages of the design process such as floorplanning, placement, or routing. Another aspect identifies or creates multiple strips or multiple regions for an area on a layer of an electronic design and assigns or associates a track pattern or a track pattern group to each of the multiple strips or multiple regions. In this latter aspect, a track pattern or a track pattern group is no longer required to apply to the entire layer.

Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design

Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.

Methods, systems, and articles of manufacture for generating multi-layer local maximal orthogonal routing paths in fractured space

An improved approach for implementing C-routing is described. Cost-based analysis is performed to balance the different rule requirements, to optimize the assignment of objects and nets during C-routing.

Method and system for utilizing hard and preferred rules for C-routing of electronic designs

Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Method, system, and program product to implement detail routing for double pattern lithography

Disclosed is a method and system for visualizing pin access locations on an integrated circuit design. Visual feedback is provided to a user that is attempting to connect a wire or a via to a pin structure polygon on the integrated circuit design. The visual feedback comprises any visual cue that provides an indication of a legal location to access the pin.

Method and system for visualizing pin access locations

Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for shapes on routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Method, system, and program product to implement C-routing for double pattern lithography

Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography using colored space tiles. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design. Colored space tiles may be utilized to perform the detail routing.

Method, system, and program product to implement colored tiles for detail routing for double pattern lithography

Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.

Growing community of inventors

Saratoga, CA, United States of America

Satish Raj