Skhynix Inc.

Dell Products Inc.

Satish Pratapneni

Wenwei Wang

Xiaofang Chen

Leroy Jones, Jr

Steven L Williams

Richard Worley

Bin Li

Noise injection systems and methods for conducting power noise susceptibility tests on memory systems, including solid state drives. A noise injection system comprises a power selector to deliver a voltage at a first or second level according to a frequency level indicated by a frequency select signal; a noise signal relay to receive a frequency noise signal and to deliver a low or high frequency noise component of the frequency noise signal according to the frequency level of the frequency select signal; and an amplification assembly, responsive to the frequency select signal and which receives the first or second level voltage based on the frequency level of the frequency select signal, receives and amplifies the high frequency noise component when the frequency select signal indicates a high frequency level, and receives and amplifies the low frequency noise component when the frequency select signal indicates a low frequency level.

Noise injection for power noise susceptibility test for memory systems

Techniques related to monitoring a health of a capacitor array of an SSD are described. In an example, a direct leakage current check is performed by determining voltages of the capacitor array at different times, computing a resistance of the capacitor array based on the voltages, and generating health data for the capacitor array based on the resistance. In another example, an indirect leakage current check is performed by determining at least one of: a number of times a voltage maintaining process is performed within a predefined time duration or a time difference between repeating the voltage maintaining process, comparing the at least one of the number of times or the time difference and a threshold, and generating the health data based on the comparison of the at least one of the number of times or the time difference and the threshold.

Health monitoring for capacitor array in storage devices

A technique for reducing electromagnetic interference (EMI) in electronic systems that provides a phase shift between signals having a common frequency component propagating on adjacent portions of circuit board signal traces. The phase shift is produced by a delay element in one of the adjacent signal traces. In one example, the delay element includes a serpentine delay located at the signal generating circuit side of the adjacent portion of the signal trace. Such a technique can be used to reduce EMI emissions from clock signals provided to RAM circuits of a system memory of a computer system.

Signal trace phase delay

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Milpitas, CA, United States of America

Satish Pratapneni