Algotochip Corporation

Dimaag-ai, Inc.

Other

Lsi Logic Corporation

Satish Padmanabhan

Pius Ng

Suresh Kadiyala

Ananth Durbha

Fuk Ho Pius Ng

Rajaram Kudli

Anand Pandurangan

Gary Oblock

Robert K Yu

Tak Shigihara

Plus Ng

Siva Selvaraj

Chakra R Srivatsa

Gomathi Sankar

Shailesh I Shah

Sanjay Banerjee

Nagarjun Pogakula Surya

Dushyanth Gokhale

Ananda Shekappa Sonnada

Anand Pandurangam

Nagarjun Pogakula Surya Prakash

James Player

The failure modes of mechanical components may be determined based on text analysis. For example, a word embedding may be determined based on a plurality of text documents that include a plurality of maintenance records characterizing failure of mechanical components. A vector representation for a particular maintenance record may then be determined based on the word embedding. Based on the vector representation, the particular maintenance record may then be identified as belonging to a particular failure mode out of a set of possible failure modes.

Failure mode discovery for machine components

A feature data segment may be determined by applying a feature segmentation model to a test data observation. The feature segmentation model may be pre-trained via a plurality of training data observations and may divide the plurality of training data observations into a plurality of feature data segments. A predicted target value may be determined by applying to a test data observation a prediction model pre-trained via a plurality of training data observations. One or more distance metrics representing a respective distance between the test data observation and the feature data segment along one or more dimensions may be determined. The one or more distance metrics may be represented in a user interface. An updated prediction model and an updated feature segmentation model that both incorporate the test data observation and the training data observations may be determined based on user input.

Detection and visualization of novel data instances for self-healing AI/ML model-based solution deployment

In many industrial settings, a process is repeated many times, for instance to transform physical inputs into physical outputs. To detect a situation involving such a process in which errors are likely to occur, information about the process may be collected to determine time-varying feature vectors. Then, a drift value may be determined by comparing feature vectors corresponding with different time periods. When the drift value crosses a designated drift threshold, a predicted outcome value may be determined by applying a prediction model. Sensitivity values may be determined for different features, and elements of the process may then be updated based at least in part on the sensitivity values.

Drift detection in static processes

Systems and methods are disclosed for training a previously trained neural network with incremental dataset. Original train data is provided to a neural network and the neural network is trained based on the plurality of classes in the sets of training data and/or testing data. The connected representation and the weights of the neural network is the model of the neural network. The trained model is to be updated for an incremental train data. The embodiments provide a process by which the trained model is updated for the incremental train data. This process creates a ground truth for the original training data and trains on the combined set of original train data and the incremental train data. The incremental training is tested on a test data to conclude the training and to generate the incremental trained model, minimizing the knowledge learned with the original data. Thus, the results remain consistent with the original model trained by the original dataset except the incremental train data.

Apparatus for knowledge based evolutionary learning in AI systems

Remaining useful life may be estimated for a machine component by training a prediction model, even when limited data from actual failures is available. Feature data such as sensor readings associated with a mechanical process may be collected over time. Such readings may be paired with estimates of remaining useful life, for instance as extracted from unstructured text of maintenance records. Such data may be used to train and test the prediction model.

Remaining useful life prediction for machine components

Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Application driven power gating

Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Programmatic auto-convergent method for 'physical layout power hot-spot' risk aware ASIP architecture customization for performance optimization

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to computer readable code. The system receives a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed. The look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model.

Integrated data model based framework for driving design convergence from architecture optimization to physical design closure

Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement.

System, architecture and micro-architecture (SAMA) representation of an integrated circuit

Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Intelligent architecture creator

Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Architecture guided optimal system precision definition algorithm for custom integrated circuit

Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

Automatic optimal integrated circuit generator from algorithms and specification

Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Growing community of inventors

Sunnyvale, CA, United States of America

Satish Padmanabhan