University of Michigan

Arm Limited

Intel Corporation

Microsoft Technology Licensing, LLC

Microsoft Corporation

Satish Narayanasamy

Peter Chen

Stephan Diestelhorst

Wei Wang

Thomas Friedrich Wenisch

Vaibhav Gogte

Shaizeen Aga

Hong Wang

Milind Baburao Girkar

Wei Ey Li

Bradley Gene Calder

John Thomas Shen

Perry H Wang

Andrew James Edwards

Xinmin Tian

Madanlal S Musuvathi

Gerolf F Hoflehner

Roni Rosner

Zhenghao Wang

Yoav Almog

Daniel Marino

James Jordan Tigani

Naftali Schwartz

Daniel LaVery

Abhayendra Singh

Peter M Chen

A data processing apparatus includes obtain circuitry that obtains a stream of instructions. The stream of instructions includes a barrier creation instruction and a barrier inhibition instruction. Track circuitry orders sending each instruction in the stream of instructions to processing circuitry based on one or more dependencies. The track circuitry is responsive to the barrier creation instruction to cause the one or more dependencies to include one or more barrier dependencies in which pre-barrier instructions, occurring before the barrier creation instruction in the stream, are sent before post-barrier instructions, occurring after the barrier creation instruction in the stream, are sent. The track circuitry is also responsive to the barrier inhibition instruction to relax the barrier dependencies to permit post-inhibition instructions, occurring after the barrier inhibition instruction in the stream, to be sent before the pre-barrier instructions.

Instruction ordering

A system that executes private enclave functions in a secure high-performance host processor connected to an enhanced memory unit through a conventional memory bus using a packetized interface is disclosed. The logic layer of the enhanced memory unit is included in a trusted computing base (TCB) and is used to implement cryptographic functions. Storage layers of the enhanced memory unit remain outside the TCB and are used to store encrypted data and associated meta-data.

Trusted computing system with enhanced memory

A data processing system including multiple processorseach with a local cache memoryshare a main memoryunder control of a coherency controller. Store requests from a store requester which are to be serviced by data received from the main memorytrigger the coherency controllerto return exclusive rights to access the data to the store requester before the corresponding data is returned from the main memory. The store requester uses possession of the exclusive rights to access the data to permit further processing with an ordering constraint relative to the store request to proceed even though the store request has yet to be finished. The ordering constraint may be, for example, a fence instruction. The store requester in possession of the exclusive rights to access the data values ensures that the store request is finished and its results observed by any instruction as required by the ordering constraint it has released early.

Ordering constraint management within coherent memory systems

This document describes a dynamic data race detector that utilizes adaptive sampling techniques. The adaptive sampling techniques include locating threads during execution of a multi-threaded program and identifying thread-specific hot paths, thread-specific cold paths and lockset paths during execution of the program. Once these paths are identified, they are sampled, potentially at different rates. Any information gained during the sampling may be stored in a data race log, which a developer may use to correct any identified program bugs.

Sampling techniques for dynamic data-race detection

An apparatus, method and computer-readable medium provide for detecting and filtering potential race conditions. In one example, potential race conditions may be detected by determining overlap of memory accesses (e.g., read, write). Potential race conditions may be filtered as potentially benign or harmful race conditions using, for example, heuristics, comparison of output states from execution of instructions or operations in differing sequences or identifying of associated output bugs corresponding to the execution of operations in different sequences.

Machine instruction level race condition detection

Embodiments of the present invention provide a method, apparatus and system which may include splitting a dependency chain into a set of reduced-width dependency chains; mapping one or more dependency chains onto one or more clustered dependency chain processors, wherein an issue-width of one or more of the clusters is adapted to accommodate a size of the dependency chains; and/or processing in parallel a plurality of dependency chains of a trace. Other embodiments are described and claimed.

System, method and apparatus for dependency chain processing

Growing community of inventors

Ann Arbor, MI, United States of America

Satish Narayanasamy