Intel Corporation

Satish Muthiyalu

Yingwen Chen

Rajesh Poornachandran

Saurabh Gupta

Karunakara Kotary

Tao Xu

Yu Yu

Pannerkumar Rajagopal

Anil Agrawal

Meera Ganesan

Systems, apparatuses and methods may provide for technology that enables, during a boot sequence, a first set of ranks in a memory module based on a battery status and a user interface and disables, during the boot sequence, a second set of ranks in the memory module based on the battery status and the user interface. The technology may also generate a map between a system address space and a first set of banks in the first set of ranks and exclude a second set of banks in the first set of ranks from the map.

Configurable reduced memory startup

Runtime memory cell row defect detection and replacement includes detecting in a memory of a computer system operating in a runtime operating system mode, a defective row of memory cells having at least one defective cell. In response to the detection of the defective row, interrupting the operating system of the computer system and, in a runtime system maintenance mode, replacing the defective row of memory cells with a spare row of memory cells as a replacement row of memory cells. Execution of the operating system is then resumed in the runtime operating system mode Other aspects and advantages are described.

Runtime cell row replacement in a memory

Method, apparatus and systems for performing hardware-based memory migration and copy operations. Under the method, a first portion of memory in a computer system accessed via a first memory controller is migrated or copied to a second portion of memory accessed via a second memory controller using a hardware-based scheme that is implemented independent of and transparent to software running on a computer system. The memory migration and/or copy operations can be used to initialize a memory mirror configuration under which data in first and second portions of memory are mirrored, and to perform memory migration operations in which data in a first portion of memory is migrated to a second portion of memory under the control of hardware in a manner in which the memory migration can be performed during run-time without a significant reduction in performance. In addition, poison data indicating failed cache lines may be migrated or copied such that data corresponding to migrated or copied poisoned cache lines are not used.

Hardware based memory migration and resilvering

Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

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Bengaluru, India

Satish Muthiyalu