Texas Instruments Corporation

Satish M Thatte

Donald W Oxley

Timothy J McEntee

Robert W Peterson

Chung C Wang

Thomas J Bannon

Vappala John Joseph

Stephen J Ford

David L Wells

Diana M Sparacin

Edward R Perez

Han-Tzong Yuan

Theo J Powell

David Harold Bartley

Craig W Thompson

Thirumalai Sridhar

David S Ho

Robert W Bloemer

Carig W Thompson

A system and method for database management for providing support for long-term storage and retrieval of objects created by application programs written at least in part in object-oriented programming languages consists of a plurality of software modules. These modules provide data definition language translation, object management, object translation, and persistent object storage service. Such system implements an object fault capability to reduce the number of interactions between the application, the database management system, and the database.

System and method for database management supporting object-oriented

A recoverable virtual memory for a computer system takes periodic checkpoints which capture the state of the virtual memory. If a system failure occurs, the system can be rolled back to the checkpointed state and restarted. A mechanism for tracking which virtual pages are contained in the checkpointed state discards pages which have been modified since the checkpointed state was saved. Only versions of pages which are saved in the checkpointed state are used in the restore process.

Recoverable virtual memory having persistant objects

A cache hierarchy to be managed by a memory management unit (MMU) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache backed up by a virtual address cache to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache is combined with a large virtual address cache. The provision of a logical address cache enables reference count management to be done completely by the controller of the virtual address cache and the memory management processor in the MMU. Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU-MMU interface is released as soon as the access to the logical address cache is completed.

Cache hierarchy design for use in a memory management unit

A uniform memory system for use with symbolic computers has a very large virtual address space. No separate files, not directly addressable in the address space of the virtual memory, exist. A special object, the peristent root, defines memory objects which are relatively permanent, such objects being traceable by pointers from the persistent root. A tombstone mechanism is used to prevent objects from referencing deleted objects.

Computer memory system having persistent objects

Periodic checkpoints are taken of the state of a computer system and its virtual memory. If a system crash occurs, the machine state can be rolled back to the checkpoint state and normal operation restarted. Pages of virtual memory are timestamped to indicate whether they are included in the checkpoint state. Modifications made after the checkpoint time are discarded when the system state is rolled back to the saved checkpoint state. Some recordkeeping is maintained outside of the virtual memory address space in order to assist with the recovery process.

Virtual memory recovery system using persistent roots for selective

An incremental garbage collector for use in conjunction with a virtual memory, operates on selected generations of an area upon objects which are contained in a semispace, oldspace or newspace, and during the garbage collection process, all accessible objects are copied from the oldspace to the newspace. The garbage collection process occurs in four phases. In the 'flip' phase oldspace and newspace of each generation are exchanged. In the 'trace' phase, the pointers which are part of a root set of the generation being collected are traced and all oldspace objects referenced by the pointers are copied to newspace, and the pointers in the root set are updated. All copied objects are then 'scavenged' to update any pointers in the cells of the copied objects, and to copy to newspace all oldspace objects referenced by those pointers. Finally a 'cleaning oldspace' phase is performed as a low-priority background process to purge the entries for the virtual pages on which 'obsolete' pointers reside.

Incremental, multi-area, generational, copying garbage collector for use

A memory system for association with a user processor for operation independently from the user processor includes a physical memory and an interface unit for enabling the associated user processor to access the physical memory. The physical memory is represented in a virtual address space which is garbage collected in parallel with the operation of the user processor. The garbage collection process includes reference count deallocation and a garbage collection algorithm for deallocating cyclic structures not deallocated by the reference count process. The reference count process includes providing for a reference count indicating the number of pointer references to a memory block in the virtual address space. When the reference count becomes zero, and no other references to a memory block exist, the block may be freed. In the garbage collection algorithm, the virtual memory space is traced in areas, called OLDSPACE, and compactly copied into a new area, called NEWSPACE. The OLDSPACE and NEWSPACE are further scavenged to insure that all referenced blocks of memory are copied, and the remaining OLDSPACE is cleaned. The garbage collection process is performed in parallel with the operation of the user processor.

Computer memory system with parallel garbage collection independent from

A computer system is provided which enables automatic memory operations independently of a CPU. The computer system includes a virtual machine and a logical memory system which is accessed by the virtual machine through a binding register unit, enabling the virtual machine to allocate blocks and specify the length of the blocks. Data within the blocks can also be specified by the user by relative indexing with respect to a block specifier in the binding register unit. The logical memory system is controlled by a separate memory management unit which manages the physical memory of the system and which manages the memory to have the logical memory system appearance to the virtual machine.

Computer system enabling automatic memory management operations

A method and apparatus for managing a block oriented memory of the type in which each memory block has an associated reference count representing the number of pointers to it from other memory blocks and itself. Efficient and cost-effective implementation of reference counting alleviates the need for frequent garbage collection, which is an expensive operation. The apparatus includes a hash table into which the virtual addresses of blocks of memory which equal zero are maintained. When the reference count of a block increases from zero, its virtual address is removed from the table. When the reference count of a block decreases to zero, its virtual address is inserted into the table. When the table is full, a reconciliation operation is performed to identify those addresses which are contained in a set of binding registers associated with the CPU, and any address not contained in the binding registers are evacuated into a garbage buffer for subsequent garbage collection operations. The apparatus can be implemented by a cache augmented by the hash table, providing a back-up store for the cache.

Method for efficient support for reference counting

A method for compacting blocks of memory in a demand paged virtual address space which includes a plurality of virtual address pages includes identifying active and stable blocks to be compacted by defining a pointer to indicate a page of the virtual memory space, and advancing the pointer to continually indicate the page of the beginning of the available virtual memory space. As new blocks are allocated, they are located in the virtual address space beginning at the next available location of the advancing pointer. As blocks are referenced by the user, they are moved to the current location of the advancing pointer, so that, stable blocks may be collected together on stable pages and active blocks are collected together on active pages. A disk memory is provided, and periodically the pages containing collected stable blocks are 'paged-out' to it. The method improves the overall throughput of data in the memory by reducing the time waiting for disk, the time in which the CPU is delayed during frequent garbage collections, and the allocation response time. Also, the method insures efficient use of the backing store by insuring that sparsely allocated pages are not written out to disk.

Method for managing virtual memory to separate active and stable memory

A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.

Architecture and method for testing VLSI processors

A test circuit, called a universal testing block (UTB) for on-chip testing of a VLSI subsystem such as a ROM or an ALU has several modes, including test generator and test evaluator, formed on the VLSI chip. The test generator circuit includes means for applying a predetermined test pattern to an input channel of the subsystem and may be a generator for generating pseudorandom test patterns for application to the subsystem. Alternatively, the test generator may be a counter which can be selectively activated to generate a binary up-count. The UTB also has a shift register mode having a serial input and output to enable serial data to be shifted into and out of the subsystem in parallel fashion. The test evaluator circuit receives output signals from the subsystem, and includes a parallel signature analyzer to generate a signature of the subsystem after the application of the test patterns by the input circuit to indicate whether the subsystem is fault-free. Also, means are provided for evaluating the signature and for generating a signal in accordance with the evaluation indicative of whether the subsystem is fault-free.

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Richardson, TX, United States of America

Satish M Thatte