Digital Equipment Corporation

Maxtor Corporation

Compaq Computer Corporation, Inc.

Quantum Corporation

Satish L Rege

Mark F Kempf

Ronald M Edgar

Santosh K Hasani

David A Gagne

Andrew P Russo

Lih-Jyh Weng

Pak-Lung Seto

Kadangode K Ramakrishnan

Michael D Leis

Joel N Harrison

Edward T Sullivan

Bruce A Leshay

Charles M Riggle

Michael J Muchnik

Frederick R Carlson, Jr

Frederic R Carlson, Jr

R Hugo Paterson

Ramesh S Kalkunte

Ramsesh Kalkunte

A data recording device including recording media having a set of at least two alternate regions thereon for each data segment, whereby each data segment has a corresponding set of at least two alternate regions on the recording media; a transducer positionable to write data on and read data from the recording media; and a controller for recording one or more data segments on the recording media in response to one or more write commands, the controller including a selector wherein for each of said one or more data segments the selector selects one region from the set of alternate regions corresponding to that data segment and positions the transducer to write that data segment on the selected region. To reduce the access time for each write operation, the selector selects the one region from the set of alternate regions based on shortest access time required to access each of the regions in the set of alternate regions for recording data.

System and method for improved disk drive performance and reliability

A data transfer management method is provided for transferring data between nodes of a multi-node communication system. The method provides target nodes with fair opportunity to transfer data to originator nodes in the communication system. The originator node initiates data transfer by establishing a connection with one or more target nodes. The originator node signals target nodes to transfer data by generating and transmitting credit tokens over the network. Before a target node can transfer data to the originator node, it must receive and absorb at least one credit token from the originator. All credit tokens transmitted by the originator node and not absorbed by target nodes return back to the originator node. Each target node is provided with buffer credit tokens up to its quota in a rotating manner.

Fair buffer credit distribution flow control

A multimedia system for delivering multimedia content to customer premises equipment via a circuit of a communications network includes a plurality of servers connected to a plurality of disk systems by a switch and a local area network. The switch includes an arbiter and a plurality of switching elements connected as a crosspoint mesh. Each switching element includes one or more gates and a register connected to a first input of each gate. The arbiter can set the registers to a logical one to allow selected multimedia content to flow through the gate either from the disk systems to the servers, or from the servers to the disk systems in response to customer demands. The local area network is used to transport switching messages from the servers and the disk systems to the arbiter.

Crosspoint switched multimedia system

A storage application programming interface (SAPI) engine is included in a hard disk drive (HDD). The SAPI engine operation is based on intelligent recognition of a plurality of different data objects characterized by type and/or size. The SAPI engine assigns a SAPI descriptor to data objects during its analysis recognition process. The SAPI descriptor identifies the type of the data object, and is used by the HDD to map the data object to a unique logical object address (LOA) space of the HDD tailored to characteristics of the particular disk drive. Using the SAPI descriptor assigned by the SAPI engine enables the HDD to more efficiently store data objects being sent by applications on a host computing system to the disk drive. The efficient storage by the HDD provides a system having improved access performance.

Method and apparatus for storage application programming interface for

A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Real time parser for data packets in a communications network

A multimedia system for delivering multimedia content items to customer premises equipment via a circuit of a communications network includes a plurality of substantially identical nodes connected in a symmetric mesh. Each node includes a switch and a server. The server includes disk storage for the multimedia content, a switch interface for connecting the server to the switch, and a network adapter for connecting the server to the communications network. Source nodes fetch data from disk, routing nodes transport data among nodes, and destination nodes transport the data to the communications network. The switch is a store-and-forward switch including direct memory access engine for pulling data into the switch, and a buffer for storing data to be forwarded to another switch. Portions of each content item are distributed substantially equally over the available storage media to improve load balancing and data redundancy.

Symmetrically switched multimedia system

A method for arbitrating conflicting requests for a memory transfer in a multiport memory system including first and second memory ports. The method includes the following steps. First, monitoring the volume of memory transfer requests from the first memory port. Second, partially disabling the second memory port if the memory request volume is greater than a first predetermined volume. And third, reenabling the second memory port when the memory request volume becomes less than a second predetermined volume. Apparatus implementing this method which includes an activity detector, coupled to the first memory port, for generating a bistate signal having a first state when the volume of memory requests by the first memory port exceeds a first predetermined volume and a second state otherwise. Circuits are provided for selectively partially disabling memory requests from the second memory port in response to the bistate signal being in the second state.

Method and apparatus for arbitrating conflicts by monitoring number of

A network adapter with an interrupt generation circuit to minimize the number of host computer system interrupts needed to notify the host computer system that the network adapter has consumed one or more host memory buffers. The interrupt generation circuit issues an interrupt to the host computer system when the host computer system has entered both a transmit sleep state and a receive sleep state, and the network adapter has consumed a host memory buffer not processed by the host computer system. When the host computer system has no work to do with respect to transmit buffers in the host computer memory, it enters a transmit sleep state and indicates to the network adapter the last transmit buffer it processed. When the host computer system has no work to do with respect to receive buffers in the host computer memory, it enters a receive sleep state and indicates to the network adapter the last receive buffer it processed. If subsequent to both these indications, the network adapter consumes a host memory buffer that the host computer system has not processed, the interrupt generation circuit issues an interrupt to the host computer system. The network adapter further includes means for the host computer system to notify the network adapter that the host computer has produced multiple host memory buffers for the network adapter to consume.

Network adapter for interrupting host computer system in the event the

In a network adapter for a host computer, the data occupancy level of a buffer memory used to store network packets is monitored, and the occupancy level is reported to the host. The buffer memory is organized as a plurality of fixed-size pages. A memory controller uses an allocation counter to track the number of pages available to store incoming data packets, and the value of the allocation counter is compared with a programmable threshold. A data word accompanies each packet delivered to the host to indicate whether the allocation count exceeds the threshold. When the buffer memory has insufficient free space to store an incoming packet, the packet is discarded. The network adapter keeps a count of the number of discarded packets. An adapter manager microprocessor, which is part of the network adapter, reports the count to the host computer on request. The adapter manager also reports the value of the allocation count and other important network adapter variables to the host computer.

System for using three different methods to report buffer memory

An apparatus for memory management in network systems provides added margins of reliability for the receipt of vital maintenance operations protocol (MOP) and station management packets (SMP). In addition, additional overflow allocations of buffers are assigned for receipt of critical system packets which otherwise would typically be discarded in the event of a highly congested system. Thus, if a MOP or a SMP packet is received from the network when the allocated space for storing these types of packets in full, the packets are stored in the overflow allocations, and thus the critical packets are not lost.

Memory management for data transmission networks

A monitor for packets on a local area network includes a set of logic circuits implemented in a computer chip, a memory interacting with the computer chip to provide monitoring data to the logic circuits, logic for receiving a packet from the local area network, and a parser to process bits of the packet as they are received, wherein the parser uses the monitoring data in conjunction with the received bits to provide forwarding data which indicates the type of packet received. The monitor uses the forwarding data to determine whether the received packet is stored in memory, discarded, or forwarded to other host computers in the network. The monitor uses type information from the forwarding data to maintain count information of the different types of packets which may be forwarded to a host computer or a remote monitoring device.

Monitor for packets on a communications network

A method and apparatus for transferring packets of information with different attributes from a device interface to buffers in a host memory dedicated to particular attribute values or ranges of values. The apparatus consists of multiple shared data structures in the form of receive rings, each associated with memory buffers dedicated to a particular range of values for a particular packet attribute. The device interface determines which receive ring is associated with a buffer dedicated to the proper attribute value range by comparing the value of the attribute of the received packet with the values of attributes associated with the buffers of each ring. A sequencing ring is provided to store the order in which each receive ring must be accessed by the host cpu when retrieving packets. This sequencing ring ensures that the host cpu will retrieve the packets in the order in which they were received.

Attribute based multiple data structures in host for network received

A network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting is disclosed. Time critical network data is transferred between the network adapter and the host computer system by means of a high throughput data transfer circuit. The high throughput data transfer circuit is designed to provide throughput equal to the bandwidth of a high speed local area network such as the Fiber Distributed Data Interconnect. The high throughput data transfer circuit will inform the local intelligence of the network adapter if the network adapter has used up all host computer system memory allocated for storing data received from the network. Adapter management data is transferred between the network adapter and the host computer system local area network through a lower throughput data transfer circuit.

Network adapter with high throughput data transfer circuit to optimize

A disk drive system provides all required synchronization, positioning, validation, and data functions within each disk sector. All of these functions are provided within two zones, a header section and a data section. The header section includes a preamble, a synchronization character and an address field, as well as servo information for track following. The data section of each sector includes a data preamble, a data synchronization character, a bad sector bit map, the data and data redundancy information. The header section of at least one sector in a track includes a short DC-erase field, a transitionless segment which is used in synchronization. To synchronize a read/write head to the disk, the system first detects the DC-erase field. The system next searches for the header premable and synchronization character. If it finds them within predetermined times, it then looks for a valid sector address to complete the synchronization. If the system does not detect the preamble and synchronization character within the predetermined times, it looks for another DC-erase field and continues the synchronization process. After the preamble and synchronization character are found, the desired sector is located by reading the addresses of the succeeding sectors.

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Groton, MA, United States of America

Satish L Rege