Murata Manufacturing Co., Ltd.

Psemi Corporation

Satish Kumar Vangara

Antony Christopher Routledge

Gregory Szczeszynski

Xiaowu Sun

Amr Ahmed Kamel

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage Vapplied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that Vis adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust V; connecting to the gate of the power FET allows Vto be directly set.

Accurate reduced gate-drive current limiter

Circuits and methods for selectable conversion ratio power converters that include low-dropout (LDO) power supplies adapted to select voltage inputs based on the selected conversion ratio while achieving high efficiency. The LDO power supplies limit current through power FETs of power converters, thereby mitigating or eliminating potentially damaging events. In some embodiments, first and second full gate-drive LDOs have 'wired-OR' outputs which may power a target circuit such as a pre-driver (and optionally, a level-shifter) coupled to the gate of a power FET. In some embodiments, first and second reduced gate-drive LDOs have “wired-OR” outputs that may power a final driver coupled to the gate of a power FET. Some embodiments have dual full gate-drive LDOs that power a target circuit such as a pre-driver (and optionally, a level-shifter), while dual reduced gate-drive LDOs that power a final driver coupled to the gate of the power FET.

Reduced gate drive for power converter with dynamically switching ratio

Low drop-out (LDO) regulator circuits and methods that can operate at high frequencies without the adverse consequences of an oscillatory resonance effect from a capacitive load. In a first embodiment, a low pass filter (LPF) is coupled to the LDO and tuned to cancel the oscillatory resonance effect. In a second embodiment, the LPF is a second-order LPF and/or programmable. Since the tuning values of the programmable LPF may be programmatically selected, a much greater range of external capacitors values (with attendant ESR and ESL values), as well as a wider range of system parasitic capacitances, can be accommodated while maintaining system stability. Some variants of the second embodiment include an oscillation detector and filter bit control circuit that allows the tuning values of the programmable LPF to be dynamically determined and re-determined. An impedance-lowering device may be coupled to lower the impedance of the connection to the LPF.

Growing community of inventors

Woodley, United Kingdom

Satish Kumar Vangara