International Business Machines Corporation

Globalfoundries Inc.

Satish Kumar Sadasivam

Prathiba Kumar

Sangram Alapati

Puneeth A H Bhat

Shruti Saxena

Varun Mallikarjunan

Rajan Ravindran

Madhavi Gopal Valluri

Steven Wayne White

Raul Esteban Silvera

Alexander Erik Mericas

Venkat Rajeev Indukuru

Shimin Cui

Christopher M Barton

Hima B Nimmagadda

Puneeth A Bhat

Amit Dugar

Gowri Shankar Palani

Jayakumar N Sankarannair

Archana Ravindar

Biplob Mishra

Srinivasan Subramanian

Mahavi G Valluri

Kumar Prathiba

A branch prediction system includes a neuron cache and logic coupled to the neuron cache. The neuron cache includes one or more weights of a neural network model trained for one or more selected code sections, and the logic is to be used with the neuron cache to predict a target address for a branch instruction of the one or more selected code sections.

Neuron cache-based hardware branch prediction

Aspects of the invention include a compiler detecting an expression in a loop that includes elements of mixed data types. The compiler then promotes elements of a sub-expression of the expression to a same intermediate data type. The compiler then calculates the sub-expression using the elements of the same intermediate data type.

Partial data type promotion to exploit efficient vectorization in microprocessors

A processor including a processor pipeline having one or more execution units configured to execute branch instructions, a branch predictor coupled to the processor pipeline and configured to predict a branch instruction outcome, and a branch classification unit coupled to the processor pipeline and the branch prediction unit. The branch classification unit is configured to, in response to detecting a branch instruction, classify the branch instruction as at least one of the following: static taken branch, static not-taken branch, simple easy-to-predict branch, flip flop hard-to-predict (HTP) branch, dynamic HTP branch, biased positive HTP branch, biased negative HTP branch, and other HTP branch.

System and method for multi-level classification of branches

A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction outcome, a branch classification unit associated with the processor pipeline and the branch prediction unit. The branch classification unit is configured to, in response to detecting a branch instruction, classify the branch instruction as at least one of the following: a simple branch or a hard-to-predict (HTP) branch, wherein a threshold used for the classification is dynamically adjusted based on a workload of the processor.

System and method for dynamic accuracy and threshold control for branch classification

A processor including a processor pipeline having one or more execution units configured to execute branch instructions, a branch predictor coupled to the processor pipeline and configured to predict a branch instruction outcome, and a branch classification unit coupled to the processor pipeline and the branch predictor. The branch classification unit is configured to, in response to detecting a branch instruction, classify the branch instruction as at least one of the following: a simple branch and a hard-to-predict branch. The branch classification unit includes a direct mapped branch type table (BTT) and a branch classification table (BCT).

Predicting a branch instruction classified as simple or hard to predict based on a confidence counter in a branch type table

Microprocessor with multiple issue queues in a microprocessor, where at least one of the issue queues is an adjustable mode queue that can be set to act as either of a priority queue, or a regular queue, with respect to intake of new instructions and/or outflow of old instructions. A set of summary bit value(s) can be set to control whether the adjustable mode queue has instruction intake priority and/or instruction outflow priority relative to the other issue queue(s).

Priority instruction handling with optimized issue queue design

Provided is a method for predicting a target address using a set of Indirect Target TAgged GEometric (ITTAGE) tables and a target address pattern table. A branch instruction that is to be executed may be identified. A first tag for the branch instruction may be determined. The first tag may be a unique identifier that corresponds to the branch instruction. Using the tag, the branch instruction may be determined to be in a target address pattern table, and an index may be generated. A predicted target address for the branch instruction may be determined using the generated index and the largest ITTAGE table. Instructions associated with the predicted target address may be fetched.

Indirect target tagged geometric branch prediction using a set of target address pattern data

An application workload is scheduled for execution by each of one or more processing cores operating in a first mode. Performance metrics for the each of the one or more processing cores and a memory component are monitored, wherein the memory component stores data necessary for the one or more processing cores to carry out instructions to complete the scheduled workload. If performance metrics are greater than a specified threshold, a number of the one or more processing cores handling the scheduled workload is reduced. If the performance metrics are not greater than the specified threshold, whether each of the processing cores of the processor is currently handling a scheduled workload is determined. If each of the processing cores of the processor is currently handling the scheduled workload, the processor is configured to operate in a second mode.

Bandwidth aware resource optimization

Aspects of the present disclosure relate to control of speculative demand loads. In some embodiments, the method includes receiving instructions for a branch in a program, detecting the branch load is in the cache, monitoring a number of completed loads for the program, determining a cache pollution ratio of executed loads to completed loads, providing the cache pollution ratio to a branch prediction unit, and altering load instructions for the branch based on the cache pollution ratio.

Control of speculative demand loads

Aspects of the disclosure relate to a hardware processor architecture. The hardware processor architecture may include a processor cache to manage a set of instructions. The hardware processor architecture may include a hint cache to manage a set of hints associated with the set of instructions. Disclosed aspects relate to establishing a hint cache which has a set of hints associated with the set of instructions. The hint cache may be established with respect to the processor cache which has a set of instructions. The set of instructions may be accessed from the processor cache. From the hint cache, the set of hints associated with the set of instructions may be communicated. The set of instructions may be processed by the hardware processor using the set of hints associated with the set of instructions. In embodiments, static or dynamic hint cache bits can be utilized.

Hardware processor architecture having a hint cache

Disclosed aspects relate to branch predictor selection management in a pipelined microprocessor architecture. A set of selection factor data may be collected in the pipelined microprocessor architecture. The set of selection factor data may be analyzed using a perceptron-based learning technique with respect to a set of candidate branch predictors. A chosen branch predictor may be selected from the set of candidate branch predictors based on analyzing the set of selection factor data with respect to the set of candidate branch predictors using the perceptron-based learning technique. The chosen branch predictor may be invoked in the pipelined microprocessor architecture.

Branch predictor selection management

Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results.

Branch synthetic generation across multiple microarchitecture generations

Systems, methods, and computer program products relating to compiling source code to reduce memory operations during execution. A compiler receives source code. The compiler identifies an indirect access array operation in the source code. The compiler generates replacement code for the indirect access array operation. The replacement code includes a mask array and a union data structure. The compiler generates modified code. The modified code modifies the source code to include the replacement code in place of the indirect access array operation.

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Erode, India

Satish Kumar Sadasivam