International Business Machines Corporation

Satish Gupta

Leon Lumelsky

Bruce D Lucas

Steven William Tomashot

Joe C St Clair

Robert Tamlyn

Marc Segre

Nathan R Hiltebeitel

Todd Williams

Randall L Henderson

David Frederick Bantz

Kiyoshi Maruyama

Frederick Hayes Dill

Steven P Larky

Alan W Peevers

Alexander K Spencer

Steven Edward Millman

Robert L Mansfield

Timothy J Ebbers

James D Wagoner

Halil Burhan Bakoglu

Hector G Romero, Jr

Chung-wai Yue

Peter J Warter

A self-contained CD-ROM player which can be installed and used as simply as a VCR. The CD-ROM player includes a CD-ROM drive and supporting hardware and software to activate and execute a program on a CD-ROM disk. It is not necessary to explicitly issue commands to activate and use the disk. The user interface is completely intuitive and simple even for someone who is completely computer illiterate. This player allows everyone, both proficient computer users and those not so proficient, to use the vast library of CD-ROM programs that have been written for personal computers.

User friendly compact disk (CD) read only memory (ROM) player

A display control such as a virtual display adapter allows the advanced functions of a display controller to be utilized in a large area of memory in addition to the normal use in display memory. This large area of memory includes system memory, and efficient access to this large area of memory is permitted for normal system use. The display controller also functions with non-contiguous and non-resident bitmaps. The flexibility of demand-paged virtual memory is utilized for display tasks, as display bitmaps may be written to the large area of memory as well as the display memory.

Virtual display adapter

An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

Video RAM double buffer select control

An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

Video ram with external select of active serial access register

A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly. The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same. The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels. By sequentially controlling the output enables to the different rows of the addressed M by N array, the frame buffer can provide rapid access to N-1 rows after normally accessing the first one. The described architecture will work equally well for M by N other array organizations with a different size (e.g., 8 by 8, 3 by 4, 5 by 4, etc). These other configurations would of course require as many concurrently accessable memory chips or sections as there are pixels in the accessed rectangular array as will be well understood.

Frame buffer architecture capable of accessing a pixel aligned M by N

A display adapter for displaying graphics data in pixel form on a high resolution display monitor includes a digital signal processor for managing adapter resources and controlling coordinate transformations, a system storage which is divided into a first portion for storing instructions for the digital signal processor and the second portion for storing data representing information to be displayed, an input buffer for permitting asynchronous and overlapped communication between the graphics display adapter and a host computer to speed operation of the system, a pixel processor for drawing vectors and manipulating areas to be displayed on the monitor, a bit mapped frame buffer, a color palette connected to outputs of the frame buffer for providing appropriate color signals to the high resolution monitor and a cursor circuit for controlling display of a cursor on the screen on the monitor.

High resolution graphics display adapter

A method for improving the viewing quality of a CRT display image without increasing resolution of the display. With the invention disclosed herein, characters are apparently positioned at sub-pixel locations to improve the viewing quality of a CRT display image. This apparent positioning is accomplished by changing intensity values assigned to pixels on a CRT display. In the preferred embodiment, the change in intensity values is effected by linear interpolation with intensity values of neighboring pixels to yield second intensity values. These second intensity values, then, improve the viewing quality of the CRT display image.

Virtual resolution displays

The system includes a plurality of memory units each for storing a plurality of independently addressable binary bits. The units operate together in response to each common bit address to supply a bit from each unit to form an array of bits for a discrete section of a larger array. The units are interconnected through common interconnection buses and selectively actuable input and output gate connections to those buses to provide for selective shifting of bits between units to change the bit array.

Computer memory system with integrated parallel shift circuits

A technique and apparatus for augmenting a random access memory with a fast clear or reset mechanism are described. A dynamic RAM having a fast clear mechanism in accordance with the present invention includes means for coupling a digital signal onto all bit lines; and fast reset control means operative for energizing the coupling means for connecting the digital signal to all of the bit lines such that upon energizing of a selected word line, all the bits connected to the selected word line are reset to the state of the digital signal, whereby reset time of the random access memory is reduced. The present invention is especially beneficial for incorporation in a frame buffer of an all points addressable raster scan display, and in a page buffer of an all points addressable printer wherein there is a requirement for high update performance.

Growing community of inventors

Peekskill, NY, United States of America

Satish Gupta