Anvaya Solutions, Inc.

Intel Corporation

Sathyamurthi Sadhasivan

Shobha Rani Mallarapu

Srinivas Atluri

Jeffrey L Rabe

Balaji Vembu

David Wyatt

Aditya Navale

Michael W Williams

Todd M Witter

James S Coke

Robert N Murdoch

Ying Cui

David D Lent

Dahmane Dahmani

Venu Madhav Kuchibhotla

Richard W Jensen

Stephen T Rowland

Dave Smyth

Mitchell W Dale

A system and method for authenticating and enabling an electronic device in an electronic system are disclosed. A particular embodiment includes: an electronic system comprising: a protected device; a requesting device node, executing on a computing system, the requesting device node including: a device query data packet generator to generate a device query packet including data representing one or more identifiers of the protected device and a particular paired system; and an authentication key retriever to obtain an authentication key based on the device query data packet from an authentication provisioning node using an external data communication; and an obfuscation state machine of the particular paired system configured with a pre-defined quantity of state elements, a pre-defined quantity of the state elements being functional state elements, the obfuscation state machine being programmed with the authentication key to cause the obfuscation state machine to transition the protected device from an initial obfuscation state to a functional state.

System and method for authenticating and enabling an electronic device in an electronic system

A system and method to cause an obfuscated non-functional device to transition to a starting functional state using a specified number of cycles are disclosed. A particular embodiment includes: an electronic system comprising: a protected electronic device; and an embedded obfuscation unit coupled with the protected electronic device, the embedded obfuscation unit including an obfuscation state machine, the embedded obfuscation unit further including control logic to: determine an initial obfuscation state and a starting functional reset state; determine a number of traversal cycles needed to traverse through states of the obfuscation state machine from the initial obfuscation state to the starting functional reset state; and initiate a state traversal operation to traverse through states of the obfuscation state machine from the initial obfuscation state to the starting functional reset state in the determined number of traversal cycles.

System and method to cause an obfuscated non-functional device to transition to a starting functional state using a specified number of cycles

A system and method for authenticating and enabling functioning of a manufactured electronic device are disclosed. A particular embodiment includes: an obfuscation code generator to produce an obfuscation code having a first portion representing manufacturing or physical characteristics of a particular paired system and a second portion representing one or more identifiers of the particular paired system, the obfuscation code generator to use the obfuscation code to obtain an authentication key; and an obfuscation state machine configured with a pre-defined quantity of state elements, a pre-defined quantity of the state elements being functional state elements, the obfuscation state machine being programmed with the authentication key to cause the obfuscation state machine to transition a protected device from an initial obfuscation state to a functional state, the embedded active obfuscation unit being further configured to load random bit-selected values from the obfuscation code into the obfuscation state machine for the values of the state elements and to load a different set of random bit-selected obfuscation values from the obfuscation code into the obfuscation state machine for the values of the functional state elements of the obfuscation state machine, thereby causing the protected device to transition from the initial obfuscation state through a set of obfuscation states before reaching the functional state for normal operation.

System and method for authenticating and enabling functioning of a manufactured electronic device

A system and method to cause an obfuscated non-functional device to transition to a starting functional state using a specified number of cycles are disclosed. A particular embodiment includes: an electronic system comprising: a protected electronic device; and an embedded obfuscation unit coupled with the protected electronic device, the embedded obfuscation unit including an obfuscation state machine, the embedded obfuscation unit further including control logic to: obtain a randomized seed value; extract a first number of bits from the randomized seed value, the first number of bits representing an initial obfuscation state; extract a second number of bits from the randomized seed value, the second number of bits representing a starting functional reset state; determine a number of traversal cycles needed to traverse through states of the obfuscation state machine from the initial obfuscation state to the starting functional reset state; and initiate a state traversal operation to traverse through states of the obfuscation state machine from the initial obfuscation state to the starting functional reset state in the determined number of traversal cycles.

Two processing elements in a single platform may communicate securely to allow the platform to take advantage of the certain cryptographic functionality in one processing element. A first processing element, such as a bridge, may use its cryptographic functionality to request a key exchange with a second processing element, such as a graphics engine. Each processing element may include a global key which is common to the two processing elements and a unique key which is unique to each processing element. A key exchange may be established during the boot process the first time the system boots and, failing any hardware change, the same key may be used throughout the lifetime of the two processing elements. Once a secure channel is set up, any application wishing to authenticate a processing element without public-private cryptographic function may perform the authentication with the other processing element which shares a secure channel with the first processing element.

Creating secure communication channels between processing elements

A system and method for authenticating and enabling functioning of a manufactured electronic device are disclosed. A particular embodiment includes: an electronic device comprising: a protected device; and an embedded and active obfuscation unit including: an obfuscation code generator to produce an obfuscation code having a first portion representing manufacturing or physical characteristics of a particular paired system and a second portion representing one or more identifiers of the particular paired system; an authentication key retriever to use the obfuscation code to obtain an authentication key from an authorized representative using an external data communication; and an obfuscation state machine configured with a pre-defined quantity of state elements, a pre-defined quantity of the state elements being functional state elements, the obfuscation state machine being programmed with the authentication key to cause the obfuscation state machine to transition the protected device from an initial obfuscation state to a functional state.

According to one embodiment of the present invention, a method of power management for a flat panel display is disclosed. The method includes: receiving image data; determining a segment mode for the received image data; selecting a portion of the received image data corresponding to the determined segment mode; accumulating a value of the selected portion of the received image data; comparing the accumulated value to a threshold value; and generating an interrupt signal if the accumulated value exceeds the threshold value.

Real-time dynamic design of liquid crystal display (LCD) panel power management through brightness control

A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches. A memory latch data (MLAD) signal is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal. Since the same signal (CAS) is used to control when the data is driven by the DRAMs and when the data is latched by the latches, the differences in output timings, signal path delays, and loads are avoided. The use of expensive timing compensation circuits and special tuning of these circuits for each circuit board redesign is thereby avoided.

Method and apparatus for sampling data from a memory

A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.

Method and apparatus for fast DMA transfer on an industry standard

A buffer circuit for transferring data between a first slower narrower computer bus and a second wider faster computer bus which buffer circuit includes first and second buffers each capable of storing a plurality of bytes of data equivalent to the width of the second bus, a single address register for holding an address which represents data in either of the two buffers, the lowest order bit of the address register indicating to which one of the two buffers data is being written, first and second registers for storing indications of valid data in the first and second buffers, and a control circuit for controlling the filling of the first and the second buffers in accordance with the byte addresses furnished and the flushing of the first and the second buffers whenever a most significant byte of a buffer has valid data, whenever an attempt is made to write to a buffer address containing valid data, and whenever an attempt is made to load data to a buffer address different than an address in the address register so that sequences of bytes of data are typically accumulated in order in one buffer until an amount of data equal to that which may be transferred on the second wider faster bus is accumulated and then that buffer is flushed to the second wider faster bus while the other buffer is loaded with new data, and so that valid data is not overwritten even though non-sequential addresses are loaded.

Growing community of inventors

El Dorado Hills, CA, United States of America

Sathyamurthi Sadhasivan