Smart Iops, Inc.

Other

Smart Lops, Inc.

Sathishkumar Udayanarayanan

Kirankumar Muralidharan

Ashutosh Kumar Das

A memory access system includes a memory that is abstracted into data structures. The memory access system further includes a processor that generates an access request for accessing the abstracted memory by way of a structure access circuit of the memory access system. As the memory is abstracted into the data structures and the processor accesses the abstracted memory using the data structures, an addressing capability of the processor is extended. Further, the computing overhead of the processor is reduced, as the processor performs various memory operations by accessing the memory by way of the structure access circuit.

Memory access system to access abstracted memory

A system includes a controller for controlling communication between a first device and a second device connected by way of a communication interface. The controller that is associated with the first device is configured to receive a communication request from a processor of the first device for communicating with the second device. Based on the communication request, the controller is further configured to retrieve a set of instructions from an instruction memory that is associated with the first device. Further, the controller is configured to control the communication interface at each cycle of a clock signal by executing each instruction thus controlling the communication between the first and second devices at each cycle of the clock signal.

Communication interface control system

A data packet distributor (DPD) includes a memory and a data packet transmission device (DPTD) connected to the memory. The DPTD receives a first data packet and identifies a destination queue for attempting transmission of the first data packet. The attempt for transmission is unsuccessful when a second data packet associated with the identified destination queue is present in the memory or the identified destination queue is unavailable for receiving the first data packet. The DPTD stores the first data packet in the memory when the attempt is unsuccessful. The DPTD re-attempts the transmission of the first data packet to the identified destination queue at end of a time interval. The re-attempt is successful when the second data packet is absent in the memory and the identified destination queue is available for receiving the first data packet.

Low-latency data packet distributor

A printed circuit board (PCB) includes first and second integrated circuits (ICs) connected by way of write and read interfaces. The first IC includes a training circuitry for training the write and read interfaces. The first IC further includes read and write delay elements. The training circuitry trains the read and write interfaces (i.e., configures the read and write delay elements) for correcting signal skews that may be introduced by the read and write interfaces, respectively. The training circuitry configures the write delay element with a first write delay value for which there are no errors while writing data to a buffer memory of the second IC. The training circuitry configures the read delay element with a first read delay value for which there are no errors while reading the data from the buffer memory.

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Bengaluru, India

Sathishkumar Udayanarayanan