Hcl Technologies Limited

Sathish Kumar Krishnamoorthy

Manickam Muthiah

Jabeer Ahamed Mohammed Nowshath

The present disclosure relates to system(s) and method(s) for interactively controlling the course of a functional simulation of DUV/SUV. The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench generates a set of input data/packets as a stimulus to be processed by the DUV/SUV. The set of input data/packets is generated to simulate and verify the DUV/SUV. Further, the testbench identifies a pre-defined event at runtime during the simulation. Upon identification of the event, the testbench is configured to pause the simulation and transmit a notification message to a user indicating the occurrence of the event. Further, the testbench waits for a pre-defined time interval to receive one or more user inputs. The testbench further generates new stimulus based on the one or more user inputs and resumes the paused simulation with the new stimulus, thereby controlling the course of the functional simulation.

System and method for interactively controlling the course of a functional simulation

Disclosed is a system for providing an inference associated with delays in processing input data packet(s) by a Design Under Verification (DUV)/System Under Verification (SUV) characterized by maintaining timing information of the input data packet(s) is disclosed. To provide an inference, initially, an input data packet is processed by a DUV or SUV. Simultaneously, an expected data packet corresponding to the input data packet is predicted and a Unique Identifier is assigned to the expected data packet corresponding to the input data packet that entered into the DUV/SUV. After assigning the Unique Identifier, the plurality of data fields pertaining to the Unique Identifier are populated in an array of Packet Timing Entries based on a Delay Identifier (ID) and a Delay Mode. The plurality of data fields may then be used for reporting various delay statistics and operational behaviour of DUV/SUV.

System and method for providing an inference associated with delays in processing input data packet(s)

Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of input packets' copy. A comparison unit compares an actual output packet, from the set of actual output packets, with an expected output packet, from the set of expected output packets, corresponding to the actual output packet. When there is a mismatch, the actual output packet is compared with at least one subsequent expected output packet until the match is found. The diagnosing unit automatically diagnoses at least one of a packet drop error, an ordering error, an error in routing, by performing a systematic failure analysis and reports a diagnostic information and/or default diagnostic information associated with the error.

Automatic simulation failures analysis flow for functional verification

The present disclosure relates to system(s) and method(s) for generating a functional simulation's progress report simultaneously when the simulation is in progress. The system comprises a testbench and a DUV/SUV connected to the testbench. The testbench generates a set of input data/packets in order to simulate and verify the DUV/SUV. The system is configured to identify one or more components, from a set of components in the testbench. Furthermore, the system receives one or more current progress messages from the one or more components and identifies one or more component Lock-Up conditions based on the processing of the one or more current progress messages and one or more previous progress messages. Further, the system executes one or more actions to resolve the one or more component Lock-Up conditions. Furthermore, the system generates a simulation progress report, simultaneously at runtime, during the simulation.

System and method for generating a functional simulations progress report

The present disclosure relates to system(s) and method(s) for capturing transaction specific stage-wise log data corresponding to at least one of a Design Under Verification or System Under Verification (DUV/SUV). The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench is configured to generate a set of input packets to be processed by the DUV/SUV. Further, the testbench is also configured to generate corresponding expected output packets. If an expected output packet does not match the corresponding actual output packet generated by the DUV/SUV after processing the set of input packets, or if the actual output packet is not generated by the DUV/SUV (when it is expected to), the testbench is configured to capture transaction specific stage-wise log data for the corresponding expected output packet in a separate TSSW log file.

System and method for capturing transaction specific stage-wise log data

The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method may comprise processing a set of input packets by a Design Under Verification or System Under Verification (DUV/SUV) and mimicking, by a prediction unit corresponding to the DUV/SUV, functionality of the DUV/SUV. The prediction unit may be a part of a testbench and is configured to process a set of input packets to predict a set of expected output packets. In one embodiment, each expected output packet from the set of expected output packets may be attached with a Descriptive Tracking Header. The Descriptive Tracking Header corresponds to metadata associated with the expected output packet. The Descriptive Tracking Header is further updated based on the result of the comparison of the expected output packet against the corresponding actual output packet and used for the generation of simulation results summary for the purpose of simulation results analysis and failures debug.

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Chennai, India

Sathish Kumar Krishnamoorthy