Broadcom Corporation

Alpha Assembly Solutions Inc.

Dell Products Inc.

Sathish Kumar

Ramanujan K Valmiki

Alexander Garland MacInnis

Chengfuh Jeffrey Tang

Xiaodong Xie

Greg Alan Kranawetter

Sandeep Bhatia

Vivian T Hsiun

Oscar Khaselev

Siuli Sarkar

Francis Cheung

Ranjit Pandher

Lakshmanan Ramakrishnan

Anna Lifton

Sutapa Mukherjee

Remya Chandran

Pavan Vishwanath

Shamik Ghosal

Ashok Pachamuthu

Bawa Singh

Nitin Vithalbhai Desai

Rahul Raut

Monnir Boureghda

Ravi Bhatkal

Nirmalya Kumar Chaki

Lionel D'Luna

Darren Duane Neuman

Kenneth R Kindsfater

Anand Pande

Morgana De Avila Ribas

Kumaravel Palanisamy

Morgana Ribas

Nitin Desai

A sintering powder comprising: a particulate having a mean longest diameter of less than 10 microns, wherein at least some of the particles forming the particulate comprise a metal at least partially coated with a capping agent. A sintering paste and sintering film comprising the sintering powder. A method for making a sintered joint by sintering the sintering powder, paste, or film in the vicinity of two or more workpieces.

Sintering powder

An API reader reads a system application's API specification file and creates a root.yml file containing key:value pairs, in which the keys are objects, and the values are staging_object.yml files. Each staging_object.yml file includes a set of entries, with each entry including a REST operation, a REST endpoint, and a description of the operation to be performed using that entry. An intelligent API converter creates structured object.yml files based on corresponding unstructured staging_object.yml files, and replaces the staging_object.yml files of the root.yml file with the newly created object.yml files. Each object.yml file includes a plurality of entries, corresponding to the entries of the respective staging_object.yml file. Each entry of the object.yml file includes an OPERATION, a JSON payload, and a VALIDATION section. An API builder uses the root.yml file to build a REST API for the system under test which is used to automate testing of the application.

Platform agnostic library-less intelligent test automation by reverse engineering product REST API specification

Sintering paste

A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller. The system includes a system bridge controller to interface a CPU with devices internal to the system as well as peripheral devices including PCI devices and I/O devices such as RAM, ROM and flash memory devices. The system is capable of displaying video and graphics in both the high definition (HD) mode and the standard definition (SD) mode. The system may output an HDTV video while converting the HDTV video and providing as another output having an SDTV format or another HDTV format.

Video, audio and graphics decode, composite and display system

Presented herein is a system for storing macroblocks for concatenated frames. A decoder system comprises a frame buffer. The frame buffer comprises one or more rows. A particular one of the rows stores macroblocks from a plurality of frames.

Storing macroblocks for concatenated frames

A method and system for testing a memory controller are provided herein. A test sequence may be generated within the memory controller. A test output may also be generated within the memory controller, where the test output is associated with the test sequence. The test output may then be verified. The test sequence may comprise one or more of a control command, a memory address, and/or a DQM signal. The test output may be generated by a sequencer. The test output may be verified by a cyclic redundancy check (CRC) module. The test sequence may also comprise random write data. The random write data may be communicated to a memory controller write data output via a write data bus.

Custom logic BIST for memory controller

Presented herein is a system for storing macroblocks for such that all vertically, horizontally, and diagonally adjacent macroblock are stored in different banks. When fetching a block from a reference frame that overlaps four macroblocks, each of the overlapped macroblocks can be fetched substantially concurrently.

System, method, and apparatus for efficiently storing macroblocks

A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to generate displayable video, and a memory controller for transferring the compressed video data to and from an external memory. The video decoder requests to the memory controller to transfer the compressed video data using one of predetermined addressing patterns. The predetermined addressing patterns allow for more efficient transferring of the compressed video data to and from the external memory when compared to sequentially transferring a fixed number of data bytes starting at a fixed address. The use of the predetermined addressing patterns results in reading the compressed video data from the external memory in a predetermined order in a less number of clock cycles. The use of the predetermined addressing patterns also results in transferring the compressed video data over the data bus between the memory controller and the video decoder in a less number of clock cycles.

Video and graphics system with MPEG specific data transfer commands

Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

Schmoo runtime reduction and dynamic calibration based on a DLL lock value

Growing community of inventors

Bengaluru, India

Sathish Kumar