Intel Corporation

Satheesh Chellappan

Karthi R Vadivelu

Kishore Kasichainula

Sridharan Ranganathan

Anoop Mukker

Lakshminarayana Pappu

Suketu U Bhatt

David J Harriman

Kar Leong Wong

Frank Baehren

Zeeshan Sarwar

Shalini Sharma

Lay Cheng Ong

Harish G Kamat

Mikal Hunsaker

John S Howard

Darren L Abramson

Zhenyu Zhu

Srikanth Potluri

Alberto J Martinez

Chunyu Zhang

Adeel A Aslam

David Hines

Terrence Huat Hin Tan

Chee Lim Poon

Shanthanand R Kutuva

Lay Chen Ong

Chin Keat Teoh

System and techniques for selectable clock sources are described herein. An electronic device includes an oscillator for a first clock signal and a tap on an input signal line to a resonator for the oscillator. The tap enables receipt of a second clock signal from an external oscillator. The electronic device includes mode selection circuitry to receives a signal from a tap to an existing input line to the electronic device. The mode selection circuitry uses this signal to select the oscillator output as the clock source or the tap on the input signal line as the clock source.

Selectable clock sources

Techniques are provided for on-chip communication. A system implementing the techniques according to an embodiment includes a first virtual physical (vPhy) circuit couplable to a host through a vPhy interface and a second vPhy circuit couplable to a device, on the same chip as the host, through another vPhy interface. The system further includes a vPhy-to-vPhy interface between the vPhy circuits which includes signal lines to transmit a first data toggle signal from the first vPhy circuit to the second vPhy circuit, and a second data toggle signal from the second vPhy circuit to the first vPhy circuit. The first vPhy circuit is configured to generate the first data toggle signal based on a signal received from the host for transmission to the device. The second vPhy circuit is configured to generate the second data toggle signal based on signal received from the device for transmission to the host.

Virtual physical circuit for on-chip communication

Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.

Methods and apparatus to reduce audio streaming latency between audio and gigabit ethernet subsystems

Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.

Low power data processing offload using external platform component

The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes. An exemplary embodiment relates to an apparatus to validate operation of a Functional Safety (FuSa) platform through delivery of a safety warning signal, the apparatus comprising: a Safety Application to issue a safety warning signal, the safety warning signal configured for audio delivery to an audience; a transmit path in communication with the Safety Application to transmit the safety warning signal; and a digital signal processing (DSP) circuitry to communicate with the transmit path, the DSP circuitry configured to detect the safety warning signal at the transmit path, the DSP circuitry further configured to communicate the detected safety warning signal back to the Safety Application; wherein the transmit path, the Safety Application and the DSP circuitry are integrated on a System-on-Chip (SoC).

Methods, systems and apparatus to use audio return path for functional safety validation

Methods and apparatus to reduce audio streaming latency between audio and Gigabit Ethernet subsystems

Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.

Systems and methods for bypass testing

Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.

Device, system and method for providing on-chip test/debug functionality

In one example a Universal Serial Bus (USB) controller comprises at least one memory register to store one or more enumeration parameters for a USB connection with the USB controller and logic, at least partially including hardware logic, to detect a USB connection with a remote device via the USB connection, retrieve one or more connection enumeration parameters for the USB connection from the at least one memory register on the USB host controller, and implement a connection enumeration process using the one or more connection enumeration parameters retrieved from the memory register on the USB controller. Other examples may be described.

USB2 high speed connection for testing

Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information&#x2014;e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.

Device, system and method for packet processing to facilitate circuit testing

An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

Methods and apparatus to offload media streams in host devices

An override subsystem on the host side of a serial data link between the host and a peripheral detects and diagnoses link errors by comparing the states of the port's link-layer component and physical layer. An override controller accesses a data-store containing stored policies for responding to particular errors. After selecting the appropriate policy, the override controller takes control of the physical layer, the link-layer component, or both, reconfigures them according to the policy to correct the errors, and returns control of the physical layer to the host controller and link-layer component. As well as error recovery, the override subsystem may be used by applications or drivers to asynchronously manage power consumed by the link.

Override subsystems for rapid recovery from serial-link errors

In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.

Configuration arbiter for multiple controllers sharing a link interface

A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.

High speed I/O pinless structural testing

Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.

Growing community of inventors

Folsom, CA, United States of America

Satheesh Chellappan