Arm Limited

Texas Instruments Corporation

Satheesh Balasubramanian

James Dennis Dodrill

Shahid Ali

Shardendu Shekhar

Sainarayanan Karatholuvu Suryanarayanan

Manigandeshwaran Mallikeswaran

Sujan Manobar

Sujan Manohar

Various implementations described herein are directed to a system and methods for validating data points associated with an integrated circuit. In one implementation, the method may include retrieving data table associated with an integrated circuit, wherein the data table includes characterized electrical data associated with one or more cells of the integrated circuit. Further, the method may include converting the data table to one or more relative matrices. The one or more relative matrices are analyzed to determine a trend formed by entries of the one or more relative matrices. Further, the method may include determining whether one or more entries of the one or more relative matrices deviate from the trend. In response to the determination, the data table is flagged.

Error detection technique based on identifying data trend issues

Various implementations described herein are directed to a system and methods for implementing a critical path architect. In one implementation, the critical path architect may be implemented with a system having a processor and memory including instructions stored thereon that, when executed by the processor, cause the processor to analyze timing data of an integrated circuit. The timing data may include transition times for cells along paths of the integrated circuit. The instructions may cause the processor to identify instances of timing degradation for the cells along the paths of the integrated circuit. The instructions may cause the processor to recommend changes for the instances of the cells along the paths having timing degradation.

Critical path architect

A synchronizer flip-flop is provided, which is able to better respond to input values that are not provided for the necessary setup or hold times. The flip-flop includes a latch that includes inverter circuitry for producing a first signal and a signal in dependence on a value of an input signal at a node. A clocked inverter includes a first switch that is connected between a first reference voltage supply and an intermediate node and a second switch, which is connected between the intermediate node and a second reference voltage supply. The first switch is controlled by the first signal and the second switch is controlled by the second signal to produce an output signal at the intermediate node.

Synchroniser flip-flop

A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.

Method and apparatus of a level shifter circuit having a structure to reduce fall and rise path delay

A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

Growing community of inventors

Bengaluru, India

Satheesh Balasubramanian